7006S20GGB datasheet, PDF - EEWORLD Datasheet

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7006S20GGB: DescriptionDual-Port SRAM, 16KX8, 20ns, CMOS, CPGA68, 1.180 X 1.180 INCH, 0.160 INCH HEIGHT, GREEN, CERAMIC, PGA-68; Categorystorage storage; File Size183KB，20 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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7006S20GGB Overview

Dual-Port SRAM, 16KX8, 20ns, CMOS, CPGA68, 1.180 X 1.180 INCH, 0.160 INCH HEIGHT, GREEN, CERAMIC, PGA-68

7006S20GGB Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	PGA
package instruction	PGA, PGA68,11X11
Contacts	68
Reach Compliance Code	compliant
ECCN code	3A001.A.2.C
Maximum access time	20 ns
I/O type	COMMON
JESD-30 code	S-CPGA-P68
JESD-609 code	e3
length	27.889 mm
memory density	131072 bit
Memory IC Type	DUAL-PORT SRAM
memory width	8
Number of functions	1
Number of ports	2
Number of terminals	68
word count	16384 words
character code	16000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	16KX8
Output characteristics	3-STATE
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	PGA
Encapsulate equivalent code	PGA68,11X11
Package shape	SQUARE
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
power supply	5 V
Certification status	Not Qualified
Filter level	MIL-PRF-38535
Maximum seat height	2.413 mm
Maximum standby current	0.03 A
Minimum standby current	4.5 V
Maximum slew rate	0.37 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	MILITARY
Terminal surface	MATTE TIN
Terminal form	PIN/PEG
Terminal pitch	2.54 mm
Terminal location	PERPENDICULAR
Maximum time at peak reflow temperature	30
width	27.889 mm
Base Number Matches	1

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HIGH-SPEED

16K x 8 DUAL-PORT

STATIC RAM

Features

◆

IDT7006S/L

◆

Functional Block Diagram

R/W

True Dual-Ported memory cells which allow simultaneous

reads of the same memory location

High-speed access

– Military: 20/25/35/55/70ns (max.)

– Industrial: 55ns (max.)

– Commercial: 15/17/20/25/35/55ns (max.)

Low-power operation

– IDT7006S

Active: 750mW (typ.)

Standby: 5mW (typ.)

– IDT7006L

Active: 700mW (typ.)

Standby: 1mW (typ.)

IDT7006 easily expands data bus width to 16 bits or more

using the Master/Slave select when cascading more than

one device

◆

M/S = H for

BUSY

output flag on Master,

M/S = L for

BUSY

input on Slave

Busy and Interrupt Flags

On-chip port arbitration logic

Full on-chip hardware support of semaphore signaling

between ports

Fully asynchronous operation from either port

Devices are capable of withstanding greater than 2001V

electrostatic discharge

Battery backup operation—2V data retention

TTL-compatible, single 5V (±10%) power supply

Available in 68-pin PGA, quad flatpack, PLCC, and a 64-pin

TQFP

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

Green parts available, see ordering information

R/W

I/O

- I/O

I/O

Control

BUSY

13L

(1,2)

I/O

-I/O

I/O

Control

BUSY

(1,2)

Address

Decoder

MEMORY

ARRAY

Address

Decoder

13R

R/W

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

R/W

SEM

(2)

INT

NOTES:

1. (MASTER):

BUSY

is output; (SLAVE):

BUSY

is input.

BUSY

outputs and

INT

outputs are non-tri-stated push-pull.

M/S

SEM

(2)

INT

2739 drw 01

OCTOBER 2008

DSC- 2739/16

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