71V2546S100PFGI8 datasheet, PDF

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71V2546S100PFGI8: DescriptionZBT SRAM, 128KX36, 5ns, CMOS, PQFP100, 14 X 20 MM, GREEN, PLASTIC, TQFP-100; Categorystorage storage; File Size717KB，21 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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71V2546S100PFGI8 Overview

ZBT SRAM, 128KX36, 5ns, CMOS, PQFP100, 14 X 20 MM, GREEN, PLASTIC, TQFP-100

71V2546S100PFGI8 Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	QFP
package instruction	LQFP,
Contacts	100
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	5 ns
Other features	PIPELINED ARCHITECTURE
JESD-30 code	R-PQFP-G100
JESD-609 code	e3
length	20 mm
memory density	4718592 bit
Memory IC Type	ZBT SRAM
memory width	36
Humidity sensitivity level	3
Number of functions	1
Number of terminals	100
word count	131072 words
character code	128000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	128KX36
Package body material	PLASTIC/EPOXY
encapsulated code	LQFP
Package shape	RECTANGULAR
Package form	FLATPACK, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
Maximum seat height	1.6 mm
Maximum supply voltage (Vsup)	3.465 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	MATTE TIN
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	14 mm
Base Number Matches	1

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128K x 36

3.3V Synchronous ZBT™ SRAM

2.5V I/O, Burst Counter

Pipelined Outputs

◆

IDT71V2546S/XS

Features

128K x 36 memory configurations

Supports high performance system speed - 150 MHz

(3.8 ns Clock-to-Data Access)

ZBT

Feature - No dead cycles between write and read

cycles

Internally synchronized output buffer enable eliminates the

need to control

Single R/W (READ/WRITE) control pin

Positive clock-edge triggered address, data, and control

signal registers for fully pipelined applications

4-word burst capability (interleaved or linear)

Individual byte write (BW

) control (May tie active)

Three chip enables for simple depth expansion

3.3V power supply (±5%), 2.5V I/O Supply (V

DDQ)

Packaged in a JEDEC standard 100-pin plastic thin quad

flatpack (TQFP) and 119 ball grid array (BGA)

The IDT71V2546 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit)

synchronous SRAM. It is designed to eliminate dead bus cycles when

turning the bus around between reads and writes, or writes and reads.

Thus, they have been given the name ZBT

, or Zero Bus Turnaround.

Description

Address and control signals are applied to the SRAM during one clock

cycle, and two cycles later the associated data cycle occurs, be it read

or write.

The IDT71V2546 contains data I/O, address and control signal

registers. Output enable is the only asynchronous signal and can be used

to disable the outputs at any given time.

A Clock Enable (CEN) pin allows operation of the IDT71V2546 to be

suspended as long as necessary. All synchronous inputs are ignored

when (CEN) is high and the internal device registers will hold their previous

values.

There are three chip enable pins (CE

, CE

) that allow the user

to deselect the device when desired. If any one of these three are not

asserted when ADV/LD is low, no new memory operation can be initiated.

However, any pending data transfers (reads or writes) will be completed.

The data bus will tri-state two cycles after chip is deselected or a write is

initiated.

The IDT71V2546 has an on-chip burst counter. In the burst mode, the

IDT71V2546 can provide four cycles of data for a single address

presented to the SRAM. The order of the burst sequence is defined by the

LBO

input pin. The

LBO

pin selects between linear and interleaved burst

sequence. The ADV/LD signal is used to load a new external address

(ADV/LD = LOW) or increment the internal burst counter (ADV/LD =

HIGH).

The IDT71V2546 SRAM utilize IDT's latest high-performance CMOS

process and is packaged in a JEDEC standard 14mm x 20mm 100-pin

thin plastic quad flatpack (TQFP) as well as a 119 ball grid array (BGA).

Pin Description Summary

-A

, CE

CEN

CLK

ADV/

LBO

I/O

-I/O

, I/O

-I/O

, V

DDQ

Ad d re ss Inp uts

Chip Enab le s

Outp ut Enab le

Re ad /Write Sig nal

Clo ck Enab le

Ind ivid ual Byte Write Se le cts

Clo ck

Ad vance b urst ad d re ss / Lo ad ne w ad d re ss

Line ar / Inte rle ave d Burst Ord e r

S le e p Mo d e

Data Inp ut / Outp ut

Co re Po we r, I/O Po we r

Gro und

Inp ut

I/O

Sup p ly

Synchro no us

Asynchro no us

Synchro no us

N/A

Synchro no us

Static

Synchro no us

Static

5294 tb l 01

APRIL 2011

DSC-5294/07

71V2546S100PFGI8 Related Products

	71V2546S100PFGI8	71V2546S150PFGI8	71V2546S100PFGI	71V2546S133PFGI8
Description	ZBT SRAM, 128KX36, 5ns, CMOS, PQFP100, 14 X 20 MM, GREEN, PLASTIC, TQFP-100	ZBT SRAM, 128KX36, 3.8ns, CMOS, PQFP100, 14 X 20 MM, GREEN, PLASTIC, TQFP-100	ZBT SRAM, 128KX36, 5ns, CMOS, PQFP100, 14 X 20 MM, GREEN, PLASTIC, TQFP-100	ZBT SRAM, 128KX36, 4.2ns, CMOS, PQFP100, 14 X 20 MM, GREEN, PLASTIC, TQFP-100
Is it lead-free?	Lead free	Lead free	Lead free	Lead free
Is it Rohs certified?	conform to	conform to	conform to	conform to
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
Parts packaging code	QFP	QFP	QFP	QFP
package instruction	LQFP,	LQFP,	LQFP, QFP100,.63X.87	LQFP,
Contacts	100	100	100	100
Reach Compliance Code	compliant	compliant	compliant	compliant
ECCN code	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A
Maximum access time	5 ns	3.8 ns	5 ns	4.2 ns
Other features	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE
JESD-30 code	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100
JESD-609 code	e3	e3	e3	e3
length	20 mm	20 mm	20 mm	20 mm
memory density	4718592 bit	4718592 bit	4718592 bit	4718592 bit
Memory IC Type	ZBT SRAM	ZBT SRAM	ZBT SRAM	ZBT SRAM
memory width	36	36	36	36
Humidity sensitivity level	3	3	3	3
Number of functions	1	1	1	1
Number of terminals	100	100	100	100
word count	131072 words	131072 words	131072 words	131072 words
character code	128000	128000	128000	128000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C
organize	128KX36	128KX36	128KX36	128KX36
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LQFP	LQFP	LQFP	LQFP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL
Peak Reflow Temperature (Celsius)	260	260	260	260
Maximum seat height	1.6 mm	1.6 mm	1.6 mm	1.6 mm
Maximum supply voltage (Vsup)	3.465 V	3.465 V	3.465 V	3.465 V
Minimum supply voltage (Vsup)	3.135 V	3.135 V	3.135 V	3.135 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal surface	MATTE TIN	MATTE TIN	Matte Tin (Sn) - annealed	MATTE TIN
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	0.65 mm	0.65 mm	0.65 mm	0.65 mm
Terminal location	QUAD	QUAD	QUAD	QUAD
Maximum time at peak reflow temperature	30	30	30	30
width	14 mm	14 mm	14 mm	14 mm
Base Number Matches	1	1	1	1

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