Semiconductor
SD60C31/P, SD60C51/P
CMOS SINGLE-COMPONENT 8-BIT MICROCOMPUTER
Description
The AUK 60C31/P 60C51/P is a high-performance micro controller fabricated with AUK
high-density CMOS technology. The AUK CMOS technology combines the high speed and
density characteristics of MOS with the low power attributes of CMOS.
The 60C51 contains a 4K x 8 ROM, a 128 x 8 RAM, 32 I/O lines, two 16-bit counter/timers,
a five-source, two-priority level nested interrupt structure, a serial I/O port for either multi-
processor communication, I/O expansion or full duplex UART, and on-chip oscillator and
clock circuits.
In addition, the device has two software selectable modes of power reduction idle mode
and power-down mode. The idle mode freezes the CPU while allowing the RAM, timers,
serial port, and interrupt system to continue functioning.
Features
•
•
•
•
•
•
•
8-bit CPU optimized for control applications.
•
Power control modes.
Pin-to-pin compatible with intel's 80C51/80C31.
60C51 low power mask programmable ROM
•
60C31 low power CPU only
64K Program Memory Space, Data Memory space
32K programmable I/O lines.
•
Two 16bit timer/counters
High performance CMOS process.
•
5 interrupt sources.
2 Level programmable serial port
•
3.5 to 12MHz @ 5V ± 20%
Ordering Information
Type NO.
SD60C31
SD60C51
Marking
SD60C31
SD60C51
Package Code
PLCC44
PLCC44
Type NO.
SD60C31P
SD60C51P
Marking
SD60C31
SD60C51
Package Code
DIP40
DIP40
Outline Dimensions
40
0 .6 95
0 .6 85
0 .6 56
0 .6 50
(1 7.6 53 )
(1 7.3 99 )
(1 6.6 62 )
(1 6.5 10 )
0.042(1.067) 45
0.048 (1.219)
unit :
21
mm
13.4
±
0.2
1 5.24
0.695 (17.653)
0.685 (17.399)
0.656 (16.662)
0.650 (16.510)
1
20
50.7 ±0. 2
±
MIN 0.020 (0.508)
SEATING PLANE
BASE PLANE
0.5 MIN
0 .0 50 (1 .27 0)
4. 5
±
0.3
0.180 (4.572)
0.165 (4.191)
0.120 (3.048)
0.090 (2.286)
0 .6 30 (16 .0 02 )
0 .5 90 (14 .9 06 )
1 .2 2T YP
2 .5 4
1. 4
±
0. 1
0. 5
±
0. 1
PLCC44
DIP40
KSI-W001-000
3.5
±
0.3
0.2 5
15 MA
X
o
1
SD60C31/P SD60C51/P
Absolute Maximum Ratings
Characteristic
Ambient temperature under bias
Storage temperature
Voltage on any pin to Vss
Maximum I
OL
per I/O pin
Power dissipation
Rating
0 ~+70
-65 ~ +150
-0.5~Vcc + 0.5
15
1
Unit
°C
°C
V
㎃
Watt
Block Diagram
External
Interrupts
Interrupt
Control
4K
ROM
SFR
128
RAM
Timer 1
Timer 0
Counter
Input
CPU
Osc
Bus
Control
Four I/O Ports
Serial
Port
TxD
P0
P2
P1
P3
RxD
Address/Data
- F
Figure
M C 6 0 C 5 1 B lo c k D ia g ra m -
ig u r e D
60C51L Block Diagram
Description
The AUK 60C31/P 60C51/P is a high-performance micro controller fabricated with AUK
high-density CMOS technology. The AUK CMOS technology combines the high speed and
density characteristics of MOS with the low power attributes of CMOS.
The 60C51 contains a 4K×8 ROM, a 128×8 RAM, 32I/O lines, two 16-bit counter/times, a
five-source, two-priority level nested interrupt structure, a serial I/O port for either multi-
processor communication, I/O expansion or full duplex UART, and on-chip oscillator and
clock circuists.
In addition, the device has tow software selectable modes of power reduction idle mode
and powerdown mode. The idle mode freezes the CPU while allowing the RAM, times, serial
port, and interrupt system to continue functioning.
KSI-W001-000
2
SD60C31/P SD60C51/P
Pin Configuration
T2EX/P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
RxD/P3.0
TxD/P3.1
INT0/P3.2
INT1/P3.3
T0/P3.4
T1/P3.5
WR/P3.6
RD/P3.7
XTAL2
XTAL1
V
SS
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
39
38
37
36
35
34
33
32
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA/V
P P
ALE/PROG
PSEN
P2.7/A15
P2.6/A14
P2.5/A13
P2.4/A12
P2.3/A11
P2.2/A10
P2.1/A9
P2.0/A8
P1.5
P1.6
P1.7
RST
RxD/P3.0
NC
TxD/3.1
INT0/P3.2
INT1/P3.3
T0/P3.4
T1/P3.5
7
8
9
10
11
12
13
14
15
16
17
44
43
42
41
40
6
5
4
3
2
1
P1.4
P1.3
P1.2
P1.1/T2EX
P1.0/T2
NC
V
CC
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
T2/P1.0
1
40
V
CC
39
38
37
36
35
40DIP
DIP40
31
30
29
28
27
26
25
24
23
22
21
44PLCC
PLCC44
34
33
32
31
30
29
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA/V
PP
NC
ALE/PROG
PSEN
P2.7/A15
P2.6/A14
P2.5/A13
21
22
24
25
18
19
20
23
26
27
Pin Description
V
CC
: PIN 40 (DIP40), PIN 44 (PLCC44)
Supply voltage during normal, Idle and power down operations.
V
SS
: PIN 20 (DIP40), PIN 22 (PLCC44)
Circuit ground.
Port 0
: PIN 32~39 (DIP40), PIN 36~43 (PLCC44)
Port 0 is an 8bit open drain bi-directional I/O port.
Port 0 pins that have 1's
written to the them float, and in that state can be used as high impedance inputs.
Port 0 is also the multiplexed low-order address and data bus during accesses to
external program and data memory.
In this application it uses strong internal pullups when emitting 1's.
KSI-W001-000
WR/P3.6
RD/P3.7
XTAL2
XTAL1
V
SS
NC
A8/P2.0
A9/P2.1
A10/P2.2
A11/P2.3
A12/P2.4
28
3
SD60C31/P SD60C51/P
Pin Description(continued)
Port 1
: PIN 1~8 (DIP40), PIN 2~9 (PLCC44)
Port 1 is an 8-bit bi-directional I/O port with internal pullups.
Port 1 pins that have 1's written to them are pulled high by the internal pullups,
and in that
state can be used as inputs. As inputs, Port 1 pins that are externally
being pulled low will source current because of the internal pullups.
Port 2
: PIN 21~28 (DIP40), PIN 24~31 (PLCC44)
Port 2 is an 8-bit bi-directional I/O port with internal pullups. Port 2 pins that have
1's written to them are pulled high by the internal pullups, and in that state can
be used as inputs. As inputs, Port 2 pins that are externally being pulled low will
source current because of the internal pullups.
Port 2 emits the high-order address byte during fetches from external Program
Memory and during accesses to external Data Memory that use 16-bit addresses
(MOVX @ DPTR). In this application it uses strong internal pullups when emitting
1's.
During accesses to external data memory that use 8-bit addresses (MOVX @
Ri), Port 2 emits the contents of the P2 Special Function Register
Port 3
: PIN 10~17 (DIP40), PIN 13~19 (PLCC44)
Port 3 is an 8-bit bi-directional I/O port with internal pullups. Port 3 pins that have
1's written to them are pulled high by the internal pullups, and in that state can
be used as inputs. As inputs, Port 3 pins that are externally being pulled low will
source current because of the pullups.
Port 3 also serves the function of various special feature of the MCS-51 Family, as
listed below :
Port PIN
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
PIN NO.
10
11
12
13
14
15
16
17
Alternate Function
RxD (Serial input port)
TxD (Serial output port)
INT0 (external interrupt 0)
INT1 (external interrupt 1)
T0 (Timer 0 external input)
T1 (Timer 1 external input)
WR (external data memory write strobe)
RD (external data memory read strobe)
RST
: PIN 9 (DIP40), PIN 10 (PLCC44)
Reset input. A high on this pin for two machine cycles while the oscillator is
running resets the device.
An internal diffused resistor to V
SS
permits Power-On
KSI-W001-000
4
reset using only an external capacitor to V
CC
.
SD60C31/P SD60C51/P
Pin Description(continued)
ALE
: PIN 30 (DIP40), PIN 33 (PLCC44)
Address latch enable output pulse for latching the low byte of the address during
accesses to external memory.
In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency,
and may be used for external timing of clocking purposes.
Note : However, that one ALE pulse is skipped during each access to external data
memory.
If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH.
With the bit set, ALE is active only during a MOVX instruction. Otherwise, the pin
is weakly pulled high.
PSEN : PIN 29 (DIP40), PIN 32 (PLCC44)
Program store enable is the read strobe to external program memory.
When the
60C51 is executing code from external program memory, PSEN is activated twice
each machine cycle, except that two PSEN activations are skipped during each
access to external data memory. PSEN is not activated during fetches from internal
program memory.
EA
: PIN 31 (DIP40), PIN 35 (PLCC44)
External access enable.
FFFFH.
If EA is strapped to V
CC
the device executes from internal program memory unless
the program counter contains an address greater than 0FFFH.
XTAL1 : PIN 19 (DIP40), PIN 21 (PLCC44)
Input to the inverting oscillator amplifier and input to the internal clock generator
circuits.
NC
: PIN1, 12, 23, 34 (PLCC44)
Non connection pins.
XTAL2 : PIN 18 (DIP40), PIN 20(PLCC44)
Output from the inverting oscillator amplifier
EA must be strapped to V
SS
in order to enable the device
to fetch code from external program memory locations starting at 0000H up to
KSI-W001-000
5
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