531FC1387M00DG datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > oscillator> 531FC1387M00DG

531FC1387M00DG: DescriptionLVDS Output Clock Oscillator, 1387MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; Categoryoscillator; File Size215KB，12 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

531FC1387M00DG Overview

LVDS Output Clock Oscillator, 1387MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

531FC1387M00DG Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
package instruction	ROHS COMPLIANT, SMD, 6 PIN
Reach Compliance Code	unknown
Other features	TRAY
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	7%
JESD-609 code	e4
Manufacturer's serial number	531
Installation features	SURFACE MOUNT
Nominal operating frequency	1387 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	LVDS
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	0.35 ns
Maximum supply voltage	2.75 V
Minimum supply voltage	2.25 V
Nominal supply voltage	2.5 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)
Base Number Matches	1

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

EVISION

R Y S TA L

S C I L L A T O R

(XO)

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH

Networking

SD/HD video

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.1 6/07

Si530/531

Recommended Resources

Smet RL-175D storage cabinet type warm water dispenser circuit diagram

Microbial electrode assembly and measurement system

Transmitter circuit for contact combustion bridge sensor

LCD touch screen interface circuit

Frequency shift keying modulation and demodulation circuit using XR-2207

Gain programmable AC coupled differential amplifier circuit

Is Verilog now more widely used than VDHL?: RT. I was a student. Last time when I was doing an experiment, my teacher told me that when you start working, the company will require you to use Verilog. The school insists on teaching VDHL.. There ...; astwyg FPGA/CPLD

MSP430 infrared remote control design: MSP430 infrared remote control design...; zzzzer16 Embedded System

ce 4.2 error loading isr, please help!!: I loaded the isr driver of isr16550.DLL in ce4.2. However, the addresses returned to me are all after 0x80000000? Then, the isr does not work properly. isr16552.dll $(_FLATRELEASEDIR)\isr16550.dll NK ...; 小庞 Embedded System

How can I make ccs6.0.1 recognize __packet?: I am using ccs6.0.1. For project protocol compatibility, I need to use __packet, but ccs does not recognize it. Please help....; lingling Microcontroller MCU

AT32F425-Evaluation Report-Flash Read and Write 07: [i=s]This post was last edited by Viagra on 2022-4-25 23:19[/i]Brief description This series is based on the evaluation report of the Ateli-AT32F425R8T7-7 development boardUse the following routine di...; 维尔瓦 Domestic Chip Exchange

ShineBlink ultra-low-code IoT chip App remotely controls relays to connect to Gizwits Cloud: 1. Description of implemented functionsThe App remotely controls the closing and opening of a relay.2. UI Configuration DescriptionThe UI configuration code included in this example is as follows:UI =...; 毛球大大 RF/Wirelessly

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components