EEWORLDEEWORLDEEWORLD

Part Number

Search

530AC1409M00DGR

Description
LVPECL Output Clock Oscillator, 1409MHz Nom, ROHS COMPLIANT, SMD, 6 PIN
Categoryoscillator   
File Size215KB,12 Pages
ManufacturerSilicon Laboratories Inc
Environmental Compliance  
Download Datasheet Parametric View All

530AC1409M00DGR Overview

LVPECL Output Clock Oscillator, 1409MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

530AC1409M00DGR Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerSilicon Laboratories Inc
package instructionROHS COMPLIANT, SMD, 6 PIN
Reach Compliance Codeunknown
Other featuresTAPE AND REEL
maximum descent time0.35 ns
Frequency Adjustment - MechanicalNO
frequency stability7%
JESD-609 codee4
Manufacturer's serial number530
Installation featuresSURFACE MOUNT
Nominal operating frequency1409 MHz
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Oscillator typeLVPECL
physical size7.0mm x 5.0mm x 1.85mm
longest rise time0.35 ns
Maximum supply voltage3.63 V
Minimum supply voltage2.97 V
Nominal supply voltage3.3 V
surface mountYES
maximum symmetry55/45 %
Terminal surfaceNickel/Gold (Ni/Au)
Base Number Matches1
S i 5 3 0 / 5 31
R
EVISION
D
C
R Y S TA L
O
S C I L L A T O R
(XO)
(10 M H
Z T O
1.4 G H
Z
)
Features
Available with any-rate output
frequencies from 10 MHz to 945 MHz
and select frequencies to 1.4 GHz
3rd generation DSPLL
®
with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
Si5602
Ordering Information:
See page 7.
Applications
SONET/SDH
Networking
SD/HD video
Test and measurement
Clock and data recovery
FPGA/ASIC clock generation
Pin Assignments:
See page 6.
(Top View)
NC
OE
GND
1
2
3
6
5
4
V
DD
Description
The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry
to provide a low jitter clock at high frequencies. The Si530/531 is available
with any-rate output frequency from 10 to 945 MHz and select frequencies to
1400 MHz. Unlike a traditional XO, where a different crystal is required for
each output frequency, the Si530/531 uses one fixed crystal to provide a
wide range of output frequencies. This IC based approach allows the crystal
resonator to provide exceptional frequency stability and reliability. In addition,
DSPLL clock synthesis provides superior supply noise rejection, simplifying
the task of generating low jitter clocks in noisy environments typically found in
communication systems. The Si530/531 IC based XO is factory configurable
for a wide variety of user specifications including frequency, supply voltage,
output format, and temperature stability. Specific configurations are factory
programmed at time of shipment, thereby eliminating long lead times
associated with custom oscillators.
®
CLK–
CLK+
Si530 (LVDS/LVPECL/CML)
OE
NC
GND
1
2
3
6
5
4
V
DD
Functional Block Diagram
V
DD
CLK– CLK+
NC
CLK
Si530 (CMOS)
Fixed
Frequency
XO
Any-rate
10–1400 MHz
DSPLL
®
Clock
Synthesis
OE
NC
GND
1
2
3
6
5
4
V
DD
CLK–
CLK+
Si531 (LVDS/LVPECL/CML)
OE
GND
Rev. 1.1 6/07
Copyright © 2007 by Silicon Laboratories
Si530/531
Take a look at Ritu Technology's low-power test system and answer questions to win new year gifts!
[size=4][font=微软雅黑][i][size=3]Battery-powered wireless communication products, in order to save power, set various functions to time-division mode, only open when necessary, and automatically shut dow...
EEWORLD社区 Test/Measurement
Is it possible to use a mobile phone to monitor oral hygiene?
Oral hygiene is becoming more and more important. Is it possible to detect oral hygiene with a mobile phone?...
patatata Medical Electronics
How to minimize clock skew when dividing the output of a counter?
Since the system clock is 50M, I want to get a low-speed clock like 1K for other modules, so I wrote a counter frequency division. But when synthesizing, it always prompts: Warning: Found 1 node(s) in...
eeleader FPGA/CPLD
The first verdict on the infringement of the invention patent of the mobile phone baseband chip in China is released
Source: French Shield Salon Recently, Aojie Technology Co., Ltd., an IPO issuer on the Science and Technology Innovation Board, disclosed a lawsuit involving a mobile phone baseband chip invention pat...
eric_wang Talking
The most luxurious kerosene lamp in history
The designer combined modern labware with this old tool to create a design - inside the transparent test tube, the fiber wick wrapped in stainless steel is immersed in clear oil and fully absorbs the ...
xyh_521 Creative Market
Photoresistor
Is it true that as long as it is a photoresistor, it can receive infrared signals, that is, when infrared rays are irradiated, the resistance will decrease, such as the photoresistor cds5528...
井子92 Electronics Design Contest

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 1692  2046  1020  2897  170  35  42  21  59  4 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号