MF1 IC S20 05
Sawn bumped 120µm wafer addendum
Rev. 3.0 — 18 July 2007
141130
Product data sheet
PUBLIC
1. General description
The MF1 IC S20 05 is a contactless Smart Card IC designed for card IC coils following the
“Mifare card IC coil design guide” and is qualified to work properly in NXP´ reader
environment, which is built according to NXP´ specification.
This specification describes electrical, physical and dimensional properties of wafers.
2. Ordering information
Table 1.
Ordering information
Package
Name
Description
Ordering Code
Type number
MF1ICS2005W/U7D
Die on sawn wafer
9352 851 56005
3. Mechanical specification
3.1 Wafer
•
•
•
•
Diameter:
Thickness:
Flatness:
PGDW:
8”
120
µm ±
15
µm
not applicable
24892
3.2 Wafer backside
•
Material:
•
Treatment:
3.3 Chip dimensions
•
Chip size:
•
Scribe lines:
1.11 x 1.06 mm
x-line: 80
µm
y-line: 80
µm
Si
ground and stress relieve
3.4 Passivation
•
Type:
•
Material:
sandwich structure
PSG / Nitride
NXP Semiconductors
MF1 IC S20 05
Sawn bumped 120µm wafer addendum
500 nm / 600 nm
•
Thickness:
3.5 Au bump
•
•
•
•
•
Bump material:
Bump hardness:
Bump shear strength:
Bump height:
Bump height uniformity:
–
within a die:
–
within a wafer:
–
wafer to wafer:
> 99.9% pure Au
35 – 80 HV 0.005
> 70 MPa
18
µm
± 2
µm
± 3
µm
± 4
µm
± 1.5
µm
104 x 104
µm
89 x 104
µm
± 5
µm
sputtered TiW
•
Bump flatness:
•
Bump size:
–
LA, LB, VSS
1
–
TESTIO
1
•
Bump size variation:
•
Under bump metallization:
Remark:
Substrate is connected to VSS.
3.6 Fail die identification
Electronic wafer mapping covers the electrical test results and additionally the results of
mechanical/ visual inspection.
No inkdots are applied.
1.Pads VSS and TESTIO are disconnected when wafer is sawn.
141130
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 3.0 — 18 July 2007
2 of 7
NXP Semiconductors
MF1 IC S20 05
Sawn bumped 120µm wafer addendum
4. Limiting values
Table 2.
Limiting values
[1][2][3]
In accordance with the Absolute Maximum Rating System (IEC 134)
Symbol
I
IN
P
TOT
T
STOR
T
OP
V
ESD
I
LU
[1]
[2]
[3]
[4]
Parameter
Input Current
Total power dissipation per package
Storage temperature
Operating temperature
Electrostatic discharge voltage
Latch-up current
[4]
Min
-
-
-55
-25
2
±
100
Max
30
200
125
70
-
Unit
mA
mW
°C
°C
kV
mA
Stresses above one or more of the limiting values may cause permanent damage to the device
These are stress ratings only. Operation of the device at these or any other conditions above those given in
the Characteristics section of the specification is not implied
Exposure to limiting values for extended periods may affect device reliability
MIL Standard 883-C method 3015; Human body model: C = 100 pF, R = 1.5 kW
5. Characteristics
Table 3.
Symbol
f
IN
C
IN
t
W
t
RET
N
WE
[1]
[2]
[3]
Electrical characteristics
[1][2][3]
Parameter
Input frequency
Input capacitance
(LCR meter HP4258)
EEPROM write time
EEPROM data
retention
EEPROM write
endurance
22
°C,
Cp-D,
13.56 MHz, 2 V
-
10
10
5
2.9
-
ms
years
cycles
Conditions
Min
-
14.4
Typ
13.56
16.1
Max
-
17.4
Unit
MHz
pF
Stresses above one or more of the limiting values may cause permanent damage to the device
These are stress ratings only. Operation of the device at these or any other conditions above those given in
the Characteristics section of the specification is not implied
Exposure to limiting values for extended periods may affect device reliability
141130
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 3.0 — 18 July 2007
3 of 7
NXP Semiconductors
MF1 IC S20 05
Sawn bumped 120µm wafer addendum
6. Chip orientation and bond pad locations
PAD (center) x [µm]
VSS
TESTIO
LA
Y
LB
0.0
252.2
17.4
712.4
y [µm]
0.0
602.3
596.1
0.0
(1)
(5)
(6)
LA
TESTIO
(4)
VSS
MF1ICS2005
LB
(8)
X
(7)
(2)
(3)
(1)
(2)
(3)
(4)
X - Scribeline width:
Y- Scribeline width:
Chip step, x -length:
Chip step, y -length:
80 µm
80 µm
1.11 mm
1.06 mm
(5)
(6)
(7)
(8)
LA
LA
LB
LB
bump
bump
bump
bump
edge
edge
edge
edge
to
to
to
to
chip
chip
chip
chip
edge,
edge,
edge,
edge,
y-length: 106.5 µm
x-length: 103.0 µm
y-length: 133.4 µm
x-length: 88.6 µm
Fig 1. Chip orientation and bond pad locations
141130
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 3.0 — 18 July 2007
4 of 7
NXP Semiconductors
MF1 IC S20 05
Sawn bumped 120µm wafer addendum
7. References
•
•
•
•
•
Data sheet “General wafer specification for 8” wafers”
Data sheet “Standard card IC MF1 IC S50 memory contents after test”
Data sheet “Standard card IC MF1 IC S50 functional Specification”
Product qualification package “Standard card IC MF1 IC S50 05”
Application note “Mifare‚ card IC coil design guide”
8. Revision history
Table 4.
141130
Modifications:
Revision history
Data sheet status
Product data sheet
Change notice
Supersedes
July 2007
Document ID Release date
•
•
The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP
Semiconductors.
Legal texts have been adapted to the new company name.
141130
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 3.0 — 18 July 2007
5 of 7
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