NB4N121KMNR2 datasheet, PDF - EEWORLD Datasheet

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NB4N121KMNR2: Description3.3V Differential In 1:21 Differential Fanout Clock Driver with HCSL level Output; CategoryAnalog mixed-signal IC Drivers and interfaces; File Size144KB，9 Pages; ManufacturerON Semiconductor; Websitehttp://www.onsemi.cn

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NB4N121KMNR2 Overview

3.3V Differential In 1:21 Differential Fanout Clock Driver with HCSL level Output

NB4N121KMNR2 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	ON Semiconductor
Parts packaging code	QFN
package instruction	8 X 8 MM, QFN-52
Contacts	52
Reach Compliance Code	compli
ECCN code	EAR99
maximum delay	0.95 ns
Interface integrated circuit type	PECL TO CML TRANSLATOR
JESD-30 code	S-XQCC-N52
length	8 mm
Number of digits	1
Number of functions	1
Number of terminals	52
Maximum operating temperature	70 °C
Minimum operating temperature	-40 °C
Output latch or register	NONE
Output polarity	COMPLEMENTARY
Package body material	UNSPECIFIED
encapsulated code	HVQCCN
Package shape	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Certification status	Not Qualified
Maximum seat height	1 mm
Maximum supply voltage	3.6 V
Minimum supply voltage	3 V
Nominal supply voltage	3.3 V
surface mount	YES
Temperature level	OTHER
Terminal form	NO LEAD
Terminal pitch	0.5 mm
Terminal location	QUAD
width	8 mm

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NB4N121K

3.3V Differential 1:21

Differential Fanout Clock

Driver with HCSL level

Output

Description

http://onsemi.com

The NB4N121K is a Clock differential input fanout distribution 1 to

21 HCSL level differential outputs, optimized for ultra low

propagation delay variation. The NB4N121K is designed with HCSL

clock distribution for FBDIMM applications in mind.

Inputs can accept differential LVPECL, CML, or LVDS levels.

Single−ended LVPECL, CML, LVCMOS or LVTTL levels are

accepted with the proper V

REFAC

supply (see Figures 5, 10, 11, 12,

and 13). Clock input pins incorporate an internal 50

on die

termination resistors.

Output drive current at I

REF

(Pin 1) for 1X load is selected by

connecting to GND. To drive a 2X load, connect I

REF

to V

. See

Figure 9.

The NB4N121K specifically guarantees low output–to–output

skews. Optimal design, layout, and processing minimize skew within

a device and from device to device. System designers can take

advantage of the NB4N121K’s performance to distribute low skew

clocks across the backplane or the motherboard.

Features

QFN−52

MN SUFFIX

CASE 485M

MARKING DIAGRAM*

NB4N

121K

AWLYYWWG

•

Typical Input Clock Frequency 100, 133, 166, 200, 266, 333 and

•

400 MHz

340 ps Typical Rise and Fall Times

800 ps Typical Propagation Delay

Dtpd

100 ps Maximum Propagation Delay Variation Per Each

Differential Pair

Additive Phase RMS Jitter: 1 ps Max

Operating Range: V

= 3.0 V to 3.6 V with V

= 0 V

Differential HCSL Output Level (700 mV Peak−to−Peak)

Pb−Free Packages are Available

= Assembly Site

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

*For additional marking information, refer to

Application Note AND8002/D.

VTCLK

CLK

Q19

VTCLK

GND

REF

Q20

Figure 1. Pin Configuration

(Top View)

ORDERING INFORMATION

See detailed ordering and shipping information in the

package dimensions section on page 8 of this data sheet.

Semiconductor Components Industries, LLC, 2012

April, 2012

−

Rev. 6

Publication Order Number:

NB4N121K/D

NB4N121KMNR2 Related Products

	NB4N121KMNR2	NB4N121K	NB4N121KMN
Description	3.3V Differential In 1:21 Differential Fanout Clock Driver with HCSL level Output	3.3V Differential In 1:21 Differential Fanout Clock Driver with HCSL level Output	3.3V Differential In 1:21 Differential Fanout Clock Driver with HCSL level Output
Is it Rohs certified?	incompatible	-	incompatible
Maker	ON Semiconductor	-	ON Semiconductor
Parts packaging code	QFN	-	QFN
package instruction	8 X 8 MM, QFN-52	-	8 X 8 MM, QFN-52
Contacts	52	-	52
Reach Compliance Code	compli	-	compli
ECCN code	EAR99	-	EAR99
maximum delay	0.95 ns	-	0.95 ns
Interface integrated circuit type	PECL TO CML TRANSLATOR	-	PECL TO CML TRANSLATOR
JESD-30 code	S-XQCC-N52	-	S-XQCC-N52
length	8 mm	-	8 mm
Number of digits	1	-	1
Number of functions	1	-	1
Number of terminals	52	-	52
Maximum operating temperature	70 °C	-	70 °C
Minimum operating temperature	-40 °C	-	-40 °C
Output latch or register	NONE	-	NONE
Output polarity	COMPLEMENTARY	-	COMPLEMENTARY
Package body material	UNSPECIFIED	-	UNSPECIFIED
encapsulated code	HVQCCN	-	HVQCCN
Package shape	SQUARE	-	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	-	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Certification status	Not Qualified	-	Not Qualified
Maximum seat height	1 mm	-	1 mm
Maximum supply voltage	3.6 V	-	3.6 V
Minimum supply voltage	3 V	-	3 V
Nominal supply voltage	3.3 V	-	3.3 V
surface mount	YES	-	YES
Temperature level	OTHER	-	OTHER
Terminal form	NO LEAD	-	NO LEAD
Terminal pitch	0.5 mm	-	0.5 mm
Terminal location	QUAD	-	QUAD
width	8 mm	-	8 mm

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