IDT71P71604S200BQG datasheet, PDF

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IDT71P71604S200BQG: DescriptionDDR SRAM, 512KX36, 0.45ns, PBGA165, 13 X 15 MM, 1 MM PITCH, GREEN, FBGA-165; Categorystorage; File Size311KB，24 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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IDT71P71604S200BQG Overview

DDR SRAM, 512KX36, 0.45ns, PBGA165, 13 X 15 MM, 1 MM PITCH, GREEN, FBGA-165

IDT71P71604S200BQG Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	BGA
package instruction	13 X 15 MM, 1 MM PITCH, GREEN, FBGA-165
Contacts	165
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	0.45 ns
JESD-30 code	R-PBGA-B165
JESD-609 code	e1
length	15 mm
memory density	18874368 bit
Memory IC Type	DDR SRAM
memory width	36
Humidity sensitivity level	3
Number of functions	1
Number of terminals	165
word count	524288 words
character code	512000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	512KX36
Package body material	PLASTIC/EPOXY
encapsulated code	TBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN SILVER COPPER
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	13 mm
Base Number Matches	1

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18Mb Pipelined

DDR™II SRAM

Burst of 2

Features

Advance

Information

IDT71P71204

IDT71P71104

IDT71P71804

IDT71P71604

Description

The IDT DDRII

Burst of two SRAMs are high-speed synchronous

memories with a double-data-rate (DDR), bidirectional data port. This

scheme allows maximization of the bandwidth on the data bus by pass-

ing two data items per clock cycle. The address bus operates at single

data rate speeds, allowing the user to fan out addresses and ease

system design while maintaining maximum performance on data trans-

fers.

The DDRII has scalable output impedance on its data output bus and

echo clocks, allowing the user to tune the bus for low noise and high

performance.

All interfaces of the DDRII SRAM are HSTL, allowing speeds be-

yond SRAM devices that use any form of TTL interface. The interface

can be scaled to higher voltages (up to 1.9V) to interface with 1.8V

systems if necessary. The device has a V

DDQ

and a separate Vref,

allowing the user to designate the interface operational voltage, indepen-

dent of the device core voltage of 1.8V V

DD.

The output impedance

control allows the user to adjust the drive strength to adapt to a wide

range of loads and transmission lines.

18Mb Density (2Mx8, 2Mx9, 1Mx18, 512kx36)

Common Read and Write Data Port

Dual Echo Clock Output

2-Word Burst on all SRAM accesses

Multiplexed Address Bus

One Read or One Write request per clock cycle

DDR (Double Data Rate) Data Bus

- Two word bursts data per clock

Depth expansion through Control Logic

HSTL (1.5V) inputs that can be scaled to receive signals

from 1.4V to 1.9V.

Scalable output drivers

Can drive HSTL, 1.8V TTL or any voltage level

from 1.4V to 1.9V.

Output Impedance adjustable from 35 ohms to 70

ohms

1.8V Core Voltage (V

)

165-ball, 1.0mm pitch, 13mm x 15mm fBGA Package

JTAG Interface

Clocking

The DDRII SRAM has two sets of input clocks, namely the K,

clocks

and the C,

clocks. In addition, the DDRII has an output “echo” clock,

CQ,

CQ.

The K and

clocks are the primary device input clocks. The K clock

is used to clock in the control signals (LD, R/W and

BWx

NWx),

the

address, and the first word of the data burst during a write operation.

Functional Block Diagram

DATA

REG

(Note 1)

WRITE DRIVER

(Note3)

CTRL

LOGIC

18M

MEMORY

ARRAY

(Note1)

(Note4)

OUTPUT SELECT

SENSE AMPS

OUTPUT REG

ADD

REG

(Note2)

WRITE/READ DECODE

(Note2)

(Note1)

CLK

GEN

SELECT OUTPUT CONTROL

6112 drw 16

Notes

1) Represents 8 data signal lines for x8, 9 signal lines for x9, 18 signal lines for x18, and 36 signal lines for x36

2) Represents 20 address signal lines for x8 and x9, 19 address signal lines for x18, and 18 address signal lines for x36.

3) Represents 1 signal line for x9, 2 signal lines for x18, and four signal lines for x36. On x8 parts, the

is a “nibble write” and there are 2

signal lines.

4) Represents 16 data signal lines for x8, 18 signal lines for x9, 36 signal lines for x18, and 72 signal lines for x36.

MAY 2004

“QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc. “

DSC-6112/00

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