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74VHC541-Q100;
74VHCT541-Q100
Octal buffer/line driver; 3-state
Rev. 1 — 4 June 2013
Product data sheet
1. General description
The 74VHC541-Q100; 74VHCT541-Q100 are high-speed Si-gate CMOS devices.
The 74VHC541-Q100; 74VHCT541-Q100 are octal non-inverting buffer/line drivers with
3-state bus compatible outputs.
The output enable inputs OE0 and OE1 control the 3-state outputs.
A HIGH on OEn causes the outputs to assume a high-impedance OFF-state.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
Balanced propagation delays
All inputs have a Schmitt-trigger action
Inputs accept voltages higher than V
CC
The 74VHC541-Q100 operates with CMOS input level
The 74VHCT541-Q100 operates with TTL input level
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
Multiple package options
NXP Semiconductors
74VHC541-Q100; 74VHCT541-Q100
Octal buffer/line driver; 3-state
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74VHC541D-Q100
74VHCT541D-Q100
74VHC541PW-Q100
74VHCT541PW-Q100
74VHC541BQ-Q100
74VHCT541BQ-Q100
40 C
to +125
C
40 C
to +125
C
TSSOP20
40 C
to +125
C
Name
SO20
Description
plastic small outline package; 20 leads;
body width 7.5 mm
Version
SOT163-1
Type number
plastic thin shrink small outline package; 20 leads; SOT360-1
body width 4.4 mm
SOT764-1
DHVQFN20 plastic dual-in-line compatible thermal enhanced
very thin quad flat package; no leads; 20
terminals; body 2.5
4.5
0.85 mm
4. Functional diagram
A0
Y0
2
18
3
A1
Y1
17
4
A2
Y2
16
5
A3
Y3
15
6
A4
Y4
14
1
19
&
EN
18
17
16
15
14
13
12
11
mna180
7
A5
Y5
13
2
3
8
A6
Y6
12
4
5
9
A7
Y7
11
6
7
OE0
1
19
OE1
mna179
8
9
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
74VHC_VHCT541_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 4 June 2013
2 of 17
NXP Semiconductors
74VHC541-Q100; 74VHCT541-Q100
Octal buffer/line driver; 3-state
5. Pinning information
5.1 Pinning
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 3.
Pin configuration SO20, TSSOP20
Fig 4.
Pin configuration DHVQFN20
5.2 Pin description
Table 2.
Symbol
OE0
A[0:7]
GND
Y[0:7]
OE1
V
CC
Pin description
Pin
1
2, 3, 4, 5, 6, 7, 8, 9
10
19
20
Description
output enable input (active LOW)
data input
ground (0 V)
output enable input (active LOW)
supply voltage
18, 17, 16, 15, 14, 13, 12, 11 data output
74VHC_VHCT541_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 4 June 2013
3 of 17
NXP Semiconductors
74VHC541-Q100; 74VHCT541-Q100
Octal buffer/line driver; 3-state
6. Functional description
Table 3.
Control
OE0
L
L
X
H
[1]
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
Z = high-impedance OFF-state.
Functional table
[1]
Input
OE1
L
L
H
X
An
L
H
X
X
Output
Yn
L
H
Z
Z
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
Parameter
supply voltage
input voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
SO20 package
TSSOP20 package
DHVQFN20 package
[1]
[2]
[3]
[4]
Conditions
Min
0.5
0.5
Max
+7.0
+7.0
-
20
25
75
-
+150
500
500
500
Unit
V
V
mA
mA
mA
mA
mA
C
mW
mW
mW
V
I
<
0.5
V
V
O
<
0.5
V or V
O
> V
CC
+ 0.5 V
V
O
=
0.5
V to (V
CC
+ 0.5 V)
[1]
[1]
20
-
-
-
75
65
T
amb
=
40 C
to +125
C
[2]
[3]
[4]
-
-
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
P
tot
derates linearly with 8 mW/K above 70
C.
P
tot
derates linearly with 5.5 mW/K above 60
C.
P
tot
derates linearly with 4.5 mW/K above 60
C.
74VHC_VHCT541_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 4 June 2013
4 of 17
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