22LV10AZ-25 datasheet, PDF - EEWORLD Datasheet

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22LV10AZ-25: DescriptionCMOS Programmable Electrically Erasable Logic Device; File Size135KB，10 Pages; ManufacturerETC

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22LV10AZ-25 Overview

CMOS Programmable Electrically Erasable Logic Device

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Commercial/Industrial

PEEL™ 22LV10AZ-25 / I-35

CMOS Programmable Electrically Erasable Logic Device

Features

•

Low Voltage, Ultra Low Power Operation

- Vcc = 2.7 to 3.6 V

- Icc = 5 µA (typical) at standby

- Icc = 1.5 mA (typical) at 1 MHz

- Meets JEDEC LV Interface Spec (JESD8-B)

- 5 Volt tolerant inputs and I/O’s

CMOS Electrically Erasable Technology

- Superior factory testing

- Reprogrammable in plastic package

- Reduces retrofit and development costs

Application Versatility

- Replaces random logic

- Super set of standard PLDs

- Pin and JEDEC compatible with 22V10

- Ideal for battery powered systems

- Replaces expensive oscillators

•

Architectural Flexibility

- Enhanced architecture fits in more logic

- 133 product terms x 44 input AND array

- 12 inputs and 10 I/O pins

- 12 possible macrocell configurations

- Asynchronous clear, synchronous preset

- Independent output enables

- Programmable clock; pin 1 or p-term

- Programmable clock polarity

- 24-Pin DIP/SOIC/TSSOP and 28 Pin PLCC

- Schmitt triggers on clock and data inputs

Schmitt Trigger Inputs

- Eliminates external Schmitt trigger devices

- Ideal for encoder designs

•

General Description

The PEEL22LV10AZ is a Programmable Electrically

Erasable Logic (PEEL) SPLD (Simple Programmable

Logic Device) that operates over the supply voltage

range of 2.7V-3.6V and features ultra-low, automatic

"zero" power-down operation. The PEEL22LV10AZ is

logically and functionally similar to ICT's 5V

PEEL22CV10A and PEEL22CV10AZ. The "zero power"

(25

µA

max. I

) power-down mode makes the

PEEL22LV10AZ ideal for a broad range of battery-

powered portable equipment applications, from hand-

held

meters

PCMCIA

modems.

EE-

reprogrammability provides both the convenience of

product fast reprogramming for product development

and quick personalization in manufacturing, including

Engineering Change Orders.

Figure 1 - Pin Configuration

I/CLK

G ND

VCC

I/O

I/CLK

G ND

VCC

I/O

The differences between the PEEL22LV10AZ and

PEEL22CV10A include the addition of programmable

clock polarity, p-term clock, and Schmitt trigger input

buffers on all inputs, including the clock. Schmitt trigger

inputs allow direct input of slow signals such as

biomedical and sine waves or clocks. Like the

PEEL22CV10A, the PEEL22LV10AZ is a pin and

JEDEC compatible, logical superset of the industry

standard

PAL22V10

SPLD

Figure

The

PEEL22LV10AZ provides additional architectural

features that allow more logic to be incorporated into

the design. The PEEL22LV10AZ architecture allows it

to replace over twenty standard 24-pin DIP, SOIC,

TSSOP

and

PLCC

packages.

Figure 2 - Block Diagram

CLK MUX (O ptiona l)

4 3 2 1 28 27 26

12 13 14 15 16 17 18

I/CLK

VCC

I/O

DIP

TSSOP

I/CLK

PEEL

T M

"AND"

ARRAY

MACRO

CEL L

I/O

133 Terms

44 Inp uts

I/O

G ND

I/O

I/CLK

G ND

VCC

I/O

SP = SYNCHRONO US PRESET

AC = ASYNCHRONO US CLEAR

O E = O UTPUT ENABLE

PLCC

SOIC

04-02-037D

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