C8051F060/1/2/3/4/5/6/7
Mixed Signal ISP Flash MCU Family
Analog Peripherals
-
Two 16-Bit SAR ADCs
•
16-bit resolution
•
±0.75 LSB INL, guaranteed no missing codes
•
Programmable throughput up to 1 Msps
•
Operate as two single-ended or one differential con-
•
-
•
•
•
•
•
-
•
verter
Direct memory access; data stored in RAM without
software overhead
Data-dependent windowed interrupt generator
Programmable throughput up to 200 ksps
8 external inputs, single-ended or differential
Built-in temperature sensor
Can synchronize outputs to timers for jitter-free wave-
form generation
Programmable hysteresis/response time
High Speed 8051
µC
Core
-
Pipelined instruction architecture; executes 70% of
-
-
Memory
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4352 Bytes internal data RAM (4 k + 256)
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64 kB (C8051F060/1/2/3/4/5), 32 kB (C8051F066/7)
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Flash; In-system programmable in 512-byte sectors
External 64 kB data memory interface with multi-
plexed and non-multiplexed modes (C8051F060/2/
4/6)
instruction set in 1 or 2 system clocks
Up to 25 MIPS throughput with 25 MHz clock
Flexible Interrupt sources
10-bit SAR ADC (C8051F060/1/2/3)
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Two 12-bit DACs (C8051F060/1/2/3)
Three Analog Comparators
Digital Peripherals
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59 general purpose I/O pins (C8051F060/2/4/6)
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24 general purpose I/O pins (C8051F061/3/5/7)
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Bosch Controller Area Network (CAN 2.0B -
-
-
C8051F060/1/2/3)
Hardware SMBus™ (I2C™ Compatible), SPI™, and
two UART serial ports available concurrently
Programmable 16-bit counter/timer array with
6 capture/compare modules
5 general purpose 16-bit counter/timers
Dedicated watchdog timer; bi-directional reset pin
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Voltage Reference
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Precision VDD Monitor/Brown-Out Detector
On-Chip JTAG Debug & Boundary Scan
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On-chip debug circuitry facilitates full-speed, non-
-
-
-
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intrusive in-circuit/in-system debugging
Provides breakpoints, single-stepping, watchpoints,
stack monitor; inspect/modify memory and registers
Superior performance to emulation systems using
ICE-chips, target pods, and sockets
IEEE1149.1 compliant boundary scan
Complete development kit
-
-
Clock Sources
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Internal calibrated precision oscillator: 24.5 MHz
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External oscillator: Crystal, RC, C, or clock
Supply Voltage .......................... 2.7 to 3.6 V
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Multiple power saving sleep and shutdown modes
100-Pin and 64-Pin TQFP Packages Available
Temperature Range: -40 to +85 °C
ANALOGPERIPHERALS
16-bit
1 Msps
ADC
16-bit
1 Msps
ADC
VREF
DIGITAL I/O
C8051F060/1/2/3
CROSSBAR
CAN 2.0B
Port 0
Port 1
Port 2
Port 3
External Memory
Interface
DMA
Interface
+
+ +
UART0
UART1
SMBus
SPI Bus
PCA
Timer 0
Timer 1
Timer 2
Timer 3
Timer 4
VOLTAGE
COMPARATOR
S
12-Bit
DAC
12-Bit
DAC
-
-
-
Port 4
Port 5
Port 6
Port 7
10-bit
200ksps
ADC
AMUX
TEMP
SENSOR
C8051F060/1/2/3Only
100 pin Only
HIGH-SPEED CONTROLLER CORE
8051 CPU
(25MIPS)
22
INTERRUPTS
64/32 kB
ISP FLASH
DEBUG
CIRCUITRY
4352 B
JTAG
SRAM
CLOCK
SANITY
CIRCUIT
CONTROL
Preliminary Rev. 1.2 7/04
Copyright © 2004 by Silicon Laboratories
C8051F060/1/2/3/4/5/6/7
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
C8051F060/1/2/3/4/5/6/7
2
Rev. 1.2
C8051F060/1/2/3/4/5/6/7
Table of Contents
1. System Overview.................................................................................................... 19
1.1. CIP-51™ Microcontroller Core.......................................................................... 25
1.1.1. Fully 8051 Compatible.............................................................................. 25
1.1.2. Improved Throughput ............................................................................... 25
1.1.3. Additional Features .................................................................................. 26
1.2. On-Chip Memory............................................................................................... 27
1.3. JTAG Debug and Boundary Scan..................................................................... 28
1.4. Programmable Digital I/O and Crossbar ........................................................... 29
1.5. Programmable Counter Array ........................................................................... 30
1.6. Controller Area Network.................................................................................... 31
1.7. Serial Ports ....................................................................................................... 32
1.8. 16-Bit Analog to Digital Converters................................................................... 33
1.9. 10-Bit Analog to Digital Converter..................................................................... 34
1.10.12-bit Digital to Analog Converters................................................................... 35
1.11.Analog Comparators......................................................................................... 36
2. Absolute Maximum Ratings .................................................................................. 37
3. Global DC Electrical Characteristics .................................................................... 38
4. Pinout and Package Definitions............................................................................ 39
5. 16-Bit ADCs (ADC0 and ADC1) ............................................................................. 51
5.1. Single-Ended or Differential Operation ............................................................. 52
5.1.1. Pseudo-Differential Inputs ........................................................................ 52
5.2. Voltage Reference ............................................................................................ 53
5.3. ADC Modes of Operation.................................................................................. 54
5.3.1. Starting a Conversion............................................................................... 54
5.3.2. Tracking Modes........................................................................................ 54
5.3.3. Settling Time Requirements ..................................................................... 56
5.4. Calibration......................................................................................................... 66
5.5. ADC0 Programmable Window Detector ........................................................... 69
6. Direct Memory Access Interface (DMA0) ............................................................. 75
6.1. Writing to the Instruction Buffer......................................................................... 75
6.2. DMA0 Instruction Format .................................................................................. 76
6.3. XRAM Addressing and Setup ........................................................................... 76
6.4. Instruction Execution in Mode 0........................................................................ 77
6.5. Instruction Execution in Mode 1........................................................................ 78
6.6. Interrupt Sources .............................................................................................. 79
6.7. Data Buffer Overflow Warnings and Errors....................................................... 79
7. 10-Bit ADC (ADC2, C8051F060/1/2/3).................................................................... 87
7.1. Analog Multiplexer ............................................................................................ 88
7.2. Modes of Operation .......................................................................................... 89
7.2.1. Starting a Conversion............................................................................... 89
7.2.2. Tracking Modes........................................................................................ 90
7.2.3. Settling Time Requirements ..................................................................... 91
Rev. 1.2
3
C8051F060/1/2/3/4/5/6/7
7.3. Programmable Window Detector ...................................................................... 97
7.3.1. Window Detector In Single-Ended Mode ................................................. 99
7.3.2. Window Detector In Differential Mode.................................................... 100
8. DACs, 12-Bit Voltage Mode (DAC0 and DAC1, C8051F060/1/2/3) .................... 103
8.1. DAC Output Scheduling.................................................................................. 104
8.1.1. Update Output On-Demand ................................................................... 104
8.1.2. Update Output Based on Timer Overflow .............................................. 104
8.2. DAC Output Scaling/Justification .................................................................... 104
9. Voltage Reference 2 (C8051F060/2) .................................................................... 111
10. Voltage Reference 2 (C8051F061/3) ................................................................... 113
11. Voltage Reference 2 (C8051F064/5/6/7) .............................................................. 115
12. Comparators ......................................................................................................... 117
12.1.Comparator Inputs.......................................................................................... 119
13. CIP-51 Microcontroller ......................................................................................... 123
13.1.Instruction Set................................................................................................. 125
13.1.1.Instruction and CPU Timing ................................................................... 125
13.1.2.MOVX Instruction and Program Memory ............................................... 125
13.2.Memory Organization ..................................................................................... 130
13.2.1.Program Memory ................................................................................... 130
13.2.2.Data Memory.......................................................................................... 131
13.2.3.General Purpose Registers.................................................................... 131
13.2.4.Bit Addressable Locations...................................................................... 131
13.2.5.Stack ..................................................................................................... 131
13.2.6.Special Function Registers .................................................................... 132
13.2.6.1.SFR Paging ................................................................................... 132
13.2.6.2.Interrupts and SFR Paging ............................................................ 132
13.2.6.3.SFR Page Stack Example ............................................................. 134
13.2.7.Register Descriptions ............................................................................. 148
13.3.Interrupt Handler............................................................................................. 151
13.3.1.MCU Interrupt Sources and Vectors ...................................................... 151
13.3.2.External Interrupts.................................................................................. 151
13.3.3.Interrupt Priorities................................................................................... 153
13.3.4.Interrupt Latency .................................................................................... 153
13.3.5.Interrupt Register Descriptions............................................................... 154
13.4.Power Management Modes............................................................................ 160
13.4.1.Idle Mode ............................................................................................... 160
13.4.2.Stop Mode.............................................................................................. 161
14. Reset Sources....................................................................................................... 163
14.1.Power-on Reset.............................................................................................. 164
14.2.Power-fail Reset ............................................................................................. 164
14.3.External Reset ................................................................................................ 164
14.4.Missing Clock Detector Reset ........................................................................ 165
14.5.Comparator0 Reset ........................................................................................ 165
14.6.External CNVSTR2 Pin Reset ........................................................................ 165
14.7.Watchdog Timer Reset................................................................................... 165
4
Rev. 1.2
C8051F060/1/2/3/4/5/6/7
14.7.1.Enable/Reset WDT ................................................................................ 166
14.7.2.Disable WDT .......................................................................................... 166
14.7.3.Disable WDT Lockout ............................................................................ 166
14.7.4.Setting WDT Interval .............................................................................. 166
15. Oscillators ............................................................................................................. 171
15.1.Programmable Internal Oscillator ................................................................... 171
15.2.External Oscillator Drive Circuit...................................................................... 173
15.3.System Clock Selection.................................................................................. 173
15.4.External Crystal Example ............................................................................... 175
15.5.External RC Example ..................................................................................... 175
15.6.External Capacitor Example ........................................................................... 175
16. Flash Memory ....................................................................................................... 177
16.1.Programming The Flash Memory ................................................................... 177
16.2.Non-volatile Data Storage .............................................................................. 178
16.3.Security Options ............................................................................................. 179
16.3.1.Summary of Flash Security Options....................................................... 183
17. External Data Memory Interface and On-Chip XRAM........................................ 187
17.1.Accessing XRAM............................................................................................ 187
17.1.1.16-Bit MOVX Example ........................................................................... 187
17.1.2.8-Bit MOVX Example ............................................................................. 187
17.2.Configuring the External Memory Interface .................................................... 188
17.3.Port Selection and Configuration.................................................................... 188
17.4.Multiplexed and Non-multiplexed Selection.................................................... 190
17.4.1.Multiplexed Configuration....................................................................... 190
17.4.2.Non-multiplexed Configuration............................................................... 191
17.5.Memory Mode Selection................................................................................. 192
17.5.1.Internal XRAM Only ............................................................................... 192
17.5.2.Split Mode without Bank Select.............................................................. 192
17.5.3.Split Mode with Bank Select................................................................... 193
17.5.4.External Only.......................................................................................... 193
17.6.Timing .......................................................................................................... 194
17.6.1.Non-multiplexed Mode ........................................................................... 196
17.6.1.1.16-bit MOVX: EMI0CF[4:2] = ‘101’, ‘110’, or ‘111’......................... 196
17.6.1.2.8-bit MOVX without Bank Select: EMI0CF[4:2] = ‘101’ or ‘111’..... 197
17.6.1.3.8-bit MOVX with Bank Select: EMI0CF[4:2] = ‘110’....................... 198
17.6.2.Multiplexed Mode ................................................................................... 199
17.6.2.1.16-bit MOVX: EMI0CF[4:2] = ‘001’, ‘010’, or ‘011’......................... 199
17.6.2.2.8-bit MOVX without Bank Select: EMI0CF[4:2] = ‘001’ or ‘011’..... 200
17.6.2.3.8-bit MOVX with Bank Select: EMI0CF[4:2] = ‘010’....................... 201
18. Port Input/Output.................................................................................................. 203
18.1.Ports 0 through 3 and the Priority Crossbar Decoder..................................... 205
18.1.1.Crossbar Pin Assignment and Allocation ............................................... 205
18.1.2.Configuring the Output Modes of the Port Pins...................................... 206
18.1.3.Configuring Port Pins as Digital Inputs................................................... 207
18.1.4.Weak Pull-ups ........................................................................................ 207
Rev. 1.2
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