NXP Semiconductors
Data Sheet: Technical Data
Document Number: IMX8MMCEC
Rev. 0.2, 04/2019
MIMX8MM6DVTLZAA
MIMX8MM4DVTLZAA
MIMX8MM2DVTLZAA
MIMX8MM5DVTLZAA
MIMX8MM3DVTLZAA
MIMX8MM1DVTLZAA
i.MX 8M Mini Applications
Processor Datasheet for
Consumer Products
Package Information
Plastic Package
FCBGA 14 x 14 mm, 0.5 mm pitch
Ordering Information
See
Table 2 on page 6
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i.MX 8M Mini introduction
1. i.MX 8M Mini introduction . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2. Ordering information . . . . . . . . . . . . . . . . . . . . . . . 6
2. Modules list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1. Recommended connections for unused input/output 12
3. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1. Chip-level conditions . . . . . . . . . . . . . . . . . . . . . . 14
3.2. Power supplies requirements and restrictions . . . 22
3.3. PLL electrical characteristics . . . . . . . . . . . . . . . . 26
3.4. On-chip oscillators . . . . . . . . . . . . . . . . . . . . . . . . 27
3.6. I/O AC parameters . . . . . . . . . . . . . . . . . . . . . . . 29
3.5. General purpose I/O (GPIO) DC parameters . . . 28
3.7. Output buffer impedance parameters . . . . . . . . . 30
3.8. System modules timing . . . . . . . . . . . . . . . . . . . . 32
3.9. External peripheral interface parameters . . . . . . 33
4. Boot mode configuration . . . . . . . . . . . . . . . . . . . . . . . . 68
4.1. Boot mode configuration pins . . . . . . . . . . . . . . . 68
4.2. Boot device interface allocation . . . . . . . . . . . . . . 69
5. Package information and contact assignments . . . . . . . 70
5.1. 14 x 14 mm package information . . . . . . . . . . . . 70
5.2. DDR pin function list . . . . . . . . . . . . . . . . . . . . . . 87
6. Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
The i.MX 8M Mini applications processor represents
NXP’s latest video and audio experience combining
state-of-the-art
media-specific
features
with
high-performance processing while optimized for lowest
power consumption.
The i.MX 8M Mini family of processors features
advanced implementation of a quad Arm® Cor-
tex®-A53 core, which operates at speeds of up to
1.8 GHz. A general purpose Cortex®-M4 400 MHz
core processor is for low-power processing. The DRAM
controller supports 32-bit/16-bit LPDDR4, DDR4, and
DDR3L memory. A wide range of audio interfaces are
available, including I2S, AC97, TDM, and S/PDIF.
There are a number of other interfaces for connecting
peripherals, such as USB, PCIe, and Ethernet.
NXP reserves the right to change the production detail specifications as may be required
to permit improvements in the design of its products.
i.MX 8M Mini introduction
Table 1. Features
Subsystem
Arm Cortex-A53 MPCore platform
Features
Quad symmetric Cortex-A53 processors
• 32 KB L1 Instruction Cache
• 32 KB L1 Data Cache
• Media Processing Engine (MPE) with NEON technology supporting the Advanced
Single Instruction Multiple Data architecture:
• Floating Point Unit (FPU) with support of the VFPv4-D16 architecture
Support of 64-bit Armv8-A architecture
512 KB unified L2 cache
Arm Cortex-M4 core platform
Low power microcontroller available for customer application:
• low power standby mode
• IoT features including Weave
• Manage IR or Wireless Remote
Cortex M4 CPU:
• 16 KB L1 Instruction Cache
• 16 KB L1 Data Cache
• 256 KB tightly coupled memory (TCM)
Connectivity
One PCI Express (PCIe)
• Single lane supporting PCIe Gen2
• Dual mode operation to function as root complex or endpoint
• Integrated PHY interface
• Support L1 low power sub-state
Two USB 2.0 OTG controllers with integrated PHY interfaces:
• Spread spectrum clock support
Three Ultra Secure Digital Host Controller (uSDHC) interfaces:
• MMC 5.1 compliance with HS400 DDR signaling to support up to 400 MB/sec
• SD/SDIO 3.0 compliance with 200 MHz SDR signaling to support up to 100
MB/sec
• Support for SDXC (extended capacity)
One Gigabit Ethernet controller with support for Energy Efficient Ethernet (EEE),
Ethernet AVB, and IEEE 1588
Four Universal Asynchronous Receiver/Transmitter (UART) modules
Four I
2
C modules
Three ECSPI modules
On-chip memory
Boot ROM (256 KB)
On-chip RAM (256 KB + 32 KB)
GPIO and pin multiplexing
General-purpose input/output (GPIO) modules with interrupt capability
Input/output multiplexing controller (IOMUXC) to provide centralized pad control
Power management
Temperature sensor with programmable trip points
Flexible power domain partitioning with internal power switches to support efficient
power management
i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 0.2, 04/2019
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NXP Semiconductors
i.MX 8M Mini introduction
Table 1. Features (continued)
Subsystem
External memory interface
32/16-bit DRAM interfaces:
• LPDDR4 (up to 1.5 GHz)
• DDR4-2400
• DDR3L-1600
8-bit NAND-Flash, including support for Raw MLC/SLC devices, BCH ECC up to
62-bit, and ONFi3.2 compliance (clock rates up to 100 MHz and data rates up to 200
MB/sec)
eMMC 5.1 Flash (2 interfaces)
SPI NOR Flash (3 interfaces)
FlexSPI with support for XIP (for ME in low-power mode) and parallel read mode of
two identical FLASH devices
Multimedia
Video Processing Unit:
• 1080p60 VP9 Profile 0, 2 (10-bit)
• 1080p60 HEVC/H.265 Decoder
• 1080p60 AVC/H.264 Baseline, Main, High decoder
• 1080p60 VP8
• 1080p60 AVC/H.264 Encoder
• 1080p60 VP8
• TrustZone support
Graphic Processing Unit:
• GCNanoUltra for 3D acceleration
• GC320 for 2D acceleration
LCDIF Display Controller:
• Support up to 2 layers of overlay
• Support up to 1080p60 display through MIPI DSI
MIPI Interface:
• 4-lane MIPI CSI interface
• 4-lane MIPI DSI interface
Audio:
• S/PDIF input and output, including a new Raw Capture input mode
• Five synchronous audio interface (SAI) modules supporting I2S, AC97, TDM,
codec/DSP, and DSD interfaces, including one SAI with 8 Tx and 8 Rx lanes, one
SAI with 4 Tx and 4 Rx lanes, two SAI with 2 Tx and 2 Rx lanes, and one SAI with
1 Tx and 1Rx lane. Support over 20 channels of audio subject to I/O limitations.
• 8-Channel Pulse Density Modulation (PDM) input
System debug
Arm CoreSight debug and trace architecture
Trace Port Interface Unit (TPIU) to support off-chip real-time trace
Embedded Trace FIFO (ETF) with 4 KB internal storage to provide trace buffering
Unified trace capability for Quad Cortex-A53 and Cortex-M4 CPUs
Cross Triggering Interface (CTI)
Support for 5-pin (JTAG) debug interface
Features
i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 0.2, 04/2019
NXP Semiconductors
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i.MX 8M Mini introduction
Table 1. Features (continued)
Subsystem
Security
Features
Resource Domain Controller (RDC) supports four domains and up to eight regions of
DDR
Arm TrustZone (TZ) architecture:
• Support Arm Cortex-A53 MPCore TrustZone
On-chip RAM (OCRAM) secure region protection using OCRAM controller
High Assurance Boot (HAB)
Cryptographic acceleration and assurance (CAAM) module and Assurance Module:
• Support Widevine and PlayReady content protection
• Public Key Cryptography (PKHA) with RSA and Elliptic Curve (ECC) algorithms
• Real-time integrity checker (RTIC)
• DRM support for RSA, AES, 3DES, DES
• Side channel attack resistance
• True random number generation (RNG)
• Manufacturing protection support
Secure non-volatile storage (SNVS):
• Secure real-time clock (RTC)
Secure JTAG controller (SJC)
NOTE
The actual feature set depends on the part numbers as described in
Table 2.
Functions such as display and camera interfaces, and connectivity
interfaces, may not be enabled for specific part numbers.
i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 0.2, 04/2019
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NXP Semiconductors
i.MX 8M Mini introduction
1.1
Block diagram
Figure 1
shows the functional modules in the i.MX 8M Mini applications processor system.
Security
TrustZone
DRM Ciphers
Secure Clock
eFuse Key Storage
Main CPU Platform
Quad Cortex-A53
32 KB I-cache
NEON
32 KB D-cache
FPU
Connectivity and I/O
1 GB Ethernet
(IEEE1588, EEE, and AVB)
S/PDIF Rx and Tx
5x I2S/SAI
512 KB L2 Cache
Random Number
32 KB Secure RAM
Low Power, Security CPU
Cortex-M4
System Control
3x Smart DMA
256 KB TCM
XTAL
Multimedia
PLLs
3D Graphics: GC NanoUltra
3x Watchdog
2D Graphics: GC320
4x PWM
6x Timer
Secure JTAG
1080p60 H265, VP9 decoder
1080p60 H264, VP8 decoder
1080p60 H.264, VP8 encoder
4-lane MIPI-CSI Interface
4-lane MIPI-DSI Interface
2x eMMC 5.1/SD 3.0
LPDDR4/DDR4/DDR3L
External Memory
4x UART
16 KB I-cache
16 KB D-cache
4x I2C, 3x ECSPI
PDM
2x USB 2.0 OTG and PHY
1x PCIe 2.0 (1-lane)
NAND CTL (BCH62)
Temperature Sensor
1x FlexSPI
Figure 1. i.MX 8M Mini system block diagram
i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 0.2, 04/2019
NXP Semiconductors
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