AL1101
24-Bit Analog-to-Digital Converter
General Description
The AL1101 is a 24-bit sigma-delta
stereo analog-to-digital audio converter
using Wavefront’s ClockEZ™ technology.
With dynamic range of 107dB, simplified
interface, and low power consumption,
the AL1101 (and its companion AL1201
DAC) is a best-in-class solution for
44.1kHz and 48kHz operation.
Features
24-bit conversion
107dB dynamic range (A-wt)
0.002% THD (input = -1dBFS)
ClockEZ™ circuitry: internal PLL derives all
necessary timing signals from one external
Fs clock
¡
64X oversampling, 5
th
order 1-bit -
modulator
Applications
Digital Mixing Boards
Signal Processors
Digital Effects Boxes
Digital Recorders
Computer Sound Boards
Karaoke Systems
Car Audio Systems
64:1 linear-phase digital decimation filter
Sample rate: 24kHz to 55kHz
Digital high-pass filter
Low power: 110mW (Fs = 48kHz)
Serial output selectable: 32/24 bits/frame
Full scale differential input =
±4V
5V operation
Architecture Block diagram and Package
INL+
INL-
AGND
REF+
REF-
VD
DGND
FORMAT
16
16 pin SOIC
150 mils wide
Wavefront Semiconductor
∴
200 Scenic View Drive
∴
Cumberland, RI 02864
∴
U.S.A.
Tel: +1 401 658-3670
∴
Fax: +1 401 658-3680
∴
Email: info@wavefrontsemi.com
On the web at www.wavefrontsemi.com
1
AL1101-0305
9
INR+
INR-
MID
VA
AGND
DGND
DOUT
WDCLK
1
8
Table of Contents
General Description
………….……………………………….............………….. 1
Features
…………………………………………………………..…………….......... 1
Applications
……………………………………….........................……………... 1
Architecture Block Diagram and Package
…..………………………………. 1
Table of Contents
………………..……………………………………….............. 2
Pin Descriptions
…………………………………………………………………….. 2
Electrical Characteristics
………………………………............…...……….… 3
Recommended Operating Conditions ……..…………….……………... 3
Analog Characteristics …….............………………………………........ 3
Digital Filter Characteristics ...........………………………………........ 3
Digital Inputs ……………………….............……..….......................... 3
Output ……………………………….............……..….......................... 3
Architecture Details
…..........…………………………………………………….. 4
Differential Analog Inputs .……............…..……………………...……. 4
Single Ended Input Conditioning Circuit ……...........……… 4
Unbalanced Input Conditioning Circuit ……...........………. 4
Serial Output Interface …….............………………………………....... 5
Serial Output Interface Formats ……………............…………5
Serial Output Interface Timing ……………............……..…… 5
Digital Highpass Output Filter …..…………............…..…………...... 6
Clock Generator and PLL ……………………............…..…………...... 6
Reference and MID ……………………............…..……..........……...... 6
Power Supplies and Ground ……………………............…..………..... 6
Suggested Connections
………………………………………….………………… 7
Package Dimensions
………………………………………….…………………..... 7
Notice and Contact Information
………………………………………………... 8
Pin Descriptions
Pin#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Name
INL+
INL-
AGND
REF+
REF-
VD
DGND
FORMAT
WDCLK
DOUT
DGND
AGND
VA
MID
INR-
INR+
Pin Type
In
In
Ground
Power
Ground
Power
Ground
In
In
Out
Ground
Ground
Power
I/O
In
In
Description
Positive analog input, left channel.
Negative analog input, left channel.
Analog ground.
Positive reference, connect to V
DD
thru 1kΩ resistor,
connect 0.1µF bypass capacitor to REF-.
Negative reference, connect to GND
Digital supply, connect 0.1µF bypass capacitor to GND.
Digital ground
Format select: 0=32 bits/frame, 1=24bits/frame.
Sample frequency wordclock, 24kHz<Fs<55kHz.
Serial data output.
Digital ground.
Analog ground.
Analog supply, connect 0.1µF bypass capacitor to GND.
Mid reference, connect 0.1µF bypass capacitor to GND.
Negative analog input, right channel.
Positive analog input, right channel.
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Electrical Characteristics
Parameter
VA
VD
IA
ID
AGND
DGND
Fs
Temp
C
LOAD
Description/Condition
Analog supply voltage
Digital supply voltage
Analog supply current
Digital supply current
Analog ground
Digital ground
Sample rate
Temperature
DOUT load capacitance
1
Min
4.5
4.5
Typ
5.0
5.0
16
6
0.0
0.0
48
25
Max
5.5
5.5
Units
V
V
mA
mA
V
V
kHz
°C
pF
dB
dB
Recommended Operating Conditions
-
-
24
0
-
-
50
70
30
Analog Characteristics
Dynamic Range
THD+N
Crosstalk
Input Voltage
Input Impedance
REF Current
Power Consumption
Gain Error
CMRR
PSRR
Input = -60dBFS (A-weighted)
Input = -1dBFS
-20dBFS
-60dBFS
Input = -1dBFS
[IN+]-[IN-] fullscale
2
Interchannel match
Common mode DC bias
Differential
I
REF 3
107
-95
-84
-44
-130
±4.0
0.01
2.5
160k
130
110
±0.34
75
70
2.5
26.23k
-76
37.9
0
2.5
16.4
0.55VD
0.1VD
1
5
0.9VD
0.1VD
-0.5
0.5
21.77k
±0.025
±4.2
dB
V
dB
V
µA
mW
%
dB
dB
Hz
dB
Hz
dB
1/Fs
µs
Ω
Common mode rejection ratio
Power supply rejection ratio
4
Digital Filter Characteristics
Passband
Stopband
Group Delay
Group Delay Distortion
Highpass Filter
-3dB bandwidth
5,6
Ripple (20Hz – 21.77kHz)
Frequency
5
Attenuation
Fc
5
-0.1dB frequency
Logical “1” input voltage
Logical “0” input voltage
Input leakage current
Input capacitance
Logical
Logical
Logical
Logical
“1”
“0”
“1”
“0”
output
output
output
output
voltage
voltage
current
current
Hz
Hz
V
V
µA
pF
V
V
mA
mA
Digital Inputs
(WDCLK, FORMAT)
V
IH
V
IL
I
IN
C
IN
Output
(DOUT)
V
OH
V
OL
I
OH
I
OL
Note 1: Temp = 25°C, VA = VD = REF+ = 5V, Fs = 48kHz, F
INPUT
= 1kHz, Bandwidth = 20Hz-20kHz.
Note 2: Full scale input scales linearly with REF potential ([REF+]-[REF-]).
Note 3: REF current scales linearly with Fs.
Note 4: Temp = 25°C, VA = VD = REF+ = 5V, Fs = 48kHz, F
INPUT
= 1kHz.
Note 5: Passband, stopband, and highpass frequencies scale with Fs.
Note 6: Passband is compensated for an external single-pole 80kHz lowpass filter at analog inputs (0.26dB
at 20kHz). Compensation scales with Fs.
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3
Architecture Details
Differential Analog Inputs
The AL1101 inputs are self-biased to MID potential. Input signals larger than maximum levels
(±4V differential, or +0.5V to +4.5V at the pin) and smaller than supply voltages are output-
limited to maximum positive and negative levels in the digital section (7FFFFFH and 800000H
respectively).
The digital section of the AL1101 compensates for the passband amplitude deviation of an
external single-pole 80kHz anti-alias filter (@ Fs=48k, scaling with Fs). To remove high-
frequency noise at the differential inputs, the capacitor between the differential inputs should be
located as close as possible to the input pins.
Single-Ended Input Conditioning Circuit
MID
8Vpp
GND
2.2k
4.4k
10
µ
2.2k
4Vpp
220
Ω
4700p
*
-
To ADC
Input
-
+
2.2k
-
+
220
Ω
10
µ
MID
+
4Vpp
GND
GND
*Note: Position capacitor as close to pins as possible.
Film or high quality ceramic capacitor suggested.
If decreasing component count is an important factor, and a decrease in performance
specifications is acceptable, the AL1101 inputs may be driven unbalanced with a simple passive
component conditioning circuit. The lowpass filter has fc = 72kHz.
Unbalanced Input Conditioning Circuit
*Note: Position capacitor as close to pins as possible.
Film or high quality ceramic capacitor suggested.
The AL1101 can properly receive input logical “1” voltages of 0.55VD. This means the AL1101
can interface directly with logic signals supplied from 3.3V systems. No special interface
circuitry is required.
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4
Serial Output Interface
The AL1101 presents its two’s complement serial output data in a standard MSB-first format.
Two bitrates are provided: The 32-bits-per-frame rate (FORMAT low) is suitable for use in
systems where 256*Fs master clocks are present. The 24-bits-per-frame rate (FORMAT high) is
convenient when interfacing with circuits where 384*Fs master clocks are present.
The output sample period is defined between rising edges of wordclock (WDCLK) input.
Nominally, this is a 50% duty-cycle clock at frequency Fs, but it can be a pulse with
Ts/256 < Pulse Width < (255/256)*Ts;
Ts=1/Fs.
Left channel data output starts when WDCLK rises, and right channel data output starts Ts/2
seconds later (on falling edge of WDCLK if WDCLK has a 50% duty cycle).
The serial bits are output on the rising edge of an internally generated bitclock (whose rising
edge is aligned with rising edge of WDCLK) that runs at 64*Fs when FORMAT is low (32-bits-per-
frame), or 48*Fs when FORMAT is high (24-bits-per-frame). The data is valid
±100ns
from the
center of these bit-frames.
Serial Output Interface Formats
Left Channel
WDCLK (Fs, 50% duty cycle shown)
DOUT, 32 bits/frame
DOUT, 24 bits/frame
23
23
0
0
23
23
0
0
Right Channel
Serial Output Interface Timing
WDCLK (Fs, 50% duty cycle shown)
64Fs bitclk (internal)
LEFT
RIGHT
DOUT
VALID
100ns100ns
Ts/128
VALID
100ns100ns
VALID
100ns100ns
Ts/128
VALID
100ns100ns
Ts/64
Ts/64
WDCLK (Fs, 50% duty cycle shown)
48Fs bitclk (internal)
LEFT
RIGHT
DOUT
VALID
100ns100ns
Ts/96
VALID
100ns100ns
VALID
100ns100ns
Ts/96
VALID
100ns100ns
Ts/48
Ts/48
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