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74LV32APW

Description
OR Gate
Categorylogic   
File Size188KB,10 Pages
ManufacturerNexperia
Websitehttps://www.nexperia.com
Environmental Compliance
Download Datasheet Parametric View All

74LV32APW Overview

OR Gate

74LV32APW Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerNexperia
package instructionTSSOP-14
Reach Compliance Codecompliant
seriesLV/LV-A/LVX/H
JESD-30 codeR-PDSO-G14
JESD-609 codee4
length5 mm
Logic integrated circuit typeOR GATE
Humidity sensitivity level1
Number of functions4
Number of entries2
Number of terminals14
Maximum operating temperature125 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)260
propagation delay (tpd)20 ns
Maximum seat height1.1 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)2 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelAUTOMOTIVE
Terminal surfaceNickel/Palladium/Gold/Silver (Ni/Pd/Au/Ag)
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width4.4 mm
Base Number Matches1
74LV32A
Quad 2-input OR gate
Rev. 1 — 19 December 2018
Product data sheet
1. General description
The 74LV32A is a quad 2-input OR gate.
Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed
voltage environments.
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.
This device is fully specified for partial power down applications using I
OFF
. The I
OFF
circuitry
disables the output, preventing the potentially damaging backflow current through the device when
it is powered down.
2. Features and benefits
Wide supply voltage range from 2.0 V to 5.5 V
Maximum t
pd
of 9.5 ns at 5 V
Typical V
OL(p)
< 0.8 V at V
CC
= 3.3 V, T
amb
= 25 °C
Typical V
OH(v)
> 2.3 V at V
CC
= 3.3 V, T
amb
= 25 °C
Supports mixed-mode voltage operation on all ports
I
OFF
circuitry provides partial Power-down mode operation
Latch-up performance exceeds 250 mA per JESD 78 Class II
ESD protection:
MM: MM JESD22-A115-B exceeds 200 V
HBM: ANSI/ESDA/JEDEC JS-001 Class 3A exceeds 4 kV
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 2 kV
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range
74LV32APW
-40 °C to +125 °C
Name
TSSOP14
Description
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
Version
SOT402-1

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