HD74LV74AFP datasheet, PDF - EEWORLD Datasheet

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HD74LV74AFP: DescriptionD Flip-Flop, LV/LV-A/LVX/H Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMOS, PDSO14, SO-14; Categorylogic; File Size82KB，15 Pages; ManufacturerHitachi （Renesas ）; Websitehttp://www.renesas.com/eng/; Environmental Compliance

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HD74LV74AFP Overview

D Flip-Flop, LV/LV-A/LVX/H Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMOS, PDSO14, SO-14

HD74LV74AFP Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Hitachi （Renesas ）
Parts packaging code	SOIC
package instruction	ASOP, SOP14,.3
Contacts	14
Reach Compliance Code	unknown
series	LV/LV-A/LVX/H
JESD-30 code	R-PDSO-G14
length	10.06 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	D FLIP-FLOP
Maximum Frequency@Nom-Sup	25000000 Hz
MaximumI(ol)	0.006 A
Humidity sensitivity level	1
Number of digits	1
Number of functions	2
Number of terminals	14
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output polarity	COMPLEMENTARY
Package body material	PLASTIC/EPOXY
encapsulated code	ASOP
Encapsulate equivalent code	SOP14,.3
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, PIGGYBACK
power supply	3.3 V
Prop。Delay @ Nom-Sup	23 ns
propagation delay (tpd)	23 ns
Certification status	Not Qualified
Maximum seat height	2.2 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	2 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Trigger type	POSITIVE EDGE
width	5.5 mm
minfmax	110 MHz
Base Number Matches	1

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HD74LV74A

Dual D–type Flip Flops with Preset and Clear

ADE-205-244 (Z)

1st Edition

March 1999

Description

The HD74LV74A has independent data, preset, clear, and clock inputs Q and

outputs in a 14 pin package.

The input data is transferred to the output at the rising edge of clock pulse CLK. Low-voltage and high-

speed operation is suitable for the battery-powered products (e.g., notebook computers), and the low-power

consumption extends the battery life.

Features

•

= 2.0 V to 5.5 V operation

•

All inputs V

(Max.) = 5.5 V (@V

= 0 V to 5.5 V)

•

All outputs V

(Max.) = 5.5 V (@V

= 0 V)

•

Typical V

ground bounce < 0.8 V (@V

= 3.3 V, Ta = 25°C)

•

Typical V

undershoot > 2.3 V (@V

= 3.3 V, Ta = 25°C)

•

Output current ±6 mA (@V

= 3.0 V to 3.6 V), ±12 mA (@V

= 4.5 V to 5.5 V)

HD74LV74AFP Related Products

	HD74LV74AFP	HD74LV74AT	HD74LV74ARP
Description	D Flip-Flop, LV/LV-A/LVX/H Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMOS, PDSO14, SO-14	D Flip-Flop, LV/LV-A/LVX/H Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMOS, PDSO14, TSSOP-14	D Flip-Flop, LV/LV-A/LVX/H Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMOS, PDSO14, SO-14
Maker	Hitachi （Renesas ）	Hitachi （Renesas ）	Hitachi （Renesas ）
Parts packaging code	SOIC	TSSOP	SOIC
package instruction	ASOP, SOP14,.3	TSSOP, TSSOP14,.25	SOP, SOP14,.25
Contacts	14	14	14
Reach Compliance Code	unknown	unknown	unknown
series	LV/LV-A/LVX/H	LV/LV-A/LVX/H	LV/LV-A/LVX/H
JESD-30 code	R-PDSO-G14	R-PDSO-G14	R-PDSO-G14
length	10.06 mm	5 mm	8.65 mm
Load capacitance (CL)	50 pF	50 pF	50 pF
Logic integrated circuit type	D FLIP-FLOP	D FLIP-FLOP	D FLIP-FLOP
Maximum Frequency@Nom-Sup	25000000 Hz	25000000 Hz	25000000 Hz
MaximumI(ol)	0.006 A	0.006 A	0.006 A
Number of digits	1	1	1
Number of functions	2	2	2
Number of terminals	14	14	14
Maximum operating temperature	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C
Output polarity	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	ASOP	TSSOP	SOP
Encapsulate equivalent code	SOP14,.3	TSSOP14,.25	SOP14,.25
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, PIGGYBACK	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE
power supply	3.3 V	3.3 V	3.3 V
Prop。Delay @ Nom-Sup	23 ns	23 ns	23 ns
propagation delay (tpd)	23 ns	23 ns	23 ns
Certification status	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	2.2 mm	1.1 mm	1.75 mm
Maximum supply voltage (Vsup)	5.5 V	5.5 V	5.5 V
Minimum supply voltage (Vsup)	2 V	2 V	2 V
Nominal supply voltage (Vsup)	2.5 V	2.5 V	2.5 V
surface mount	YES	YES	YES
technology	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal form	GULL WING	GULL WING	GULL WING
Terminal pitch	1.27 mm	0.65 mm	1.27 mm
Terminal location	DUAL	DUAL	DUAL
Trigger type	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE
width	5.5 mm	4.4 mm	3.95 mm
minfmax	110 MHz	110 MHz	110 MHz
Base Number Matches	1	1	-

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