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DS3105: DescriptionLine Card Timing IC; File Size627KB，110 Pages; ManufacturerMaxim; Websitehttps://www.maximintegrated.com/en.html

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DS3105 Overview

Line Card Timing IC

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Preliminary. Subject to Change Without Notice.

PRELIMINARY DATASHEET

DS3105

Line Card Timing IC

www.maxim-ic.com

GENERAL DESCRIPTION

The DS3105 is a low-cost, feature-rich timing IC for

telecom line cards. Typically the device accepts two

reference clocks from dual redundant system timing

cards. The DS3105 continually monitors both inputs

and performs automatic hitless reference switching if

the primary reference fails. The highly programmable

DS3105 supports numerous input and output

frequencies including frequencies required for

SONET/SDH, Synchronous Ethernet (1G, 10G and

100Mb/s), wireless basestations and CMTS systems.

PLL bandwidths from 18 Hz to 400 Hz are supported,

and a wide variety of PLL characteristics and device

features can be configured to meet the needs of

many different applications.

The DS3105 register set is backward compatible with

Semtech’s ACS8525 line card timing IC. The DS3105

pinout is similar but not identical to the ACS8525.

FEATURES

Advanced DPLL Technology

Programmable PLL bandwidth: 18 Hz to 400 Hz

Hitless Reference Switching, Automatic or Manual

Holdover on Loss of All Input References

Frequency Conversion Among SONET/SDH, PDH,

Ethernet, Wireless and CMTS Rates

5 Input Clocks

Two CMOS/TTL (≤125 MHz)

Two LVDS/LVPECL/CMOS/TTL (≤156.25 MHz)

Backup Input (CMOS/TLL) in Case of Complete

Loss of System Timing References

Three Optional Frame Sync Inputs (CMOS/TTL)

Continuous Input Clock Quality Monitoring

Numerous Input Clock Frequencies Supported

- SONET/SDH: 6.48, N x 19.44, N x 51.84 MHz

- Ethernet xMII: 2.5, 25, 125, 156.25 MHz

- PDH: N x DS1, N x E1, N x DS2, DS3, E3

- Frame Sync: 2 kHz, 4 kHz, 8 kHz

- Custom:

Any Multiple of 2 kHz up to 131.072 MHz,

Any Multiple of 8 kHz up to 155.52 MHz

APPLICATIONS

SONET/SDH, Synchronous Ethernet, PDH and Other

Line Cards in WAN Equipment Including MSPPs,

Ethernet Switches, Routers, DSLAMs, and Wireless

Base Stations.

FUNCTIONAL DIAGRAM

LVDS/LVPECL

or CMOS/TTL

IC3

IC4

IC5

IC6

IC9

OC3

2 Output Clocks

One CMOS/TTL Output (≤125 MHz)

One LVDS/LVPECL Output (≤312.50 MHz)

Two Optional Frame Sync Outputs: 2 kHz, 8 kHz

Numerous Output Clock Frequencies Supported

- SONET/SDH: 6.48, N x 19.44, N x 51.84 MHz

- Ethernet xMII: 2.5, 25, 125, 156.25, 312.5 MHz

- PDH: N x DS1, N x E1, N x DS2, DS3, E3

- Other: 10, 10.24, 13, 30.72 MHz, plus other

frequencies available upon request

- Frame Sync: 2 kHz, 8 kHz

- Custom Clock Rates: Any Multiple of 2 kHz up to

77.76 MHz, Any Multiple of 8 kHz up to 311.04 MHz

DS3105

OC6 LVDS/LVPECL

SYNC1

SYNC2

SYNC3

local

oscillator

FSYNC

MFSYNC

General

Suitable line card IC for stratum 3E/3/4, SMC, SEC

Internal Compensation for Master Clock Oscillator

SPI Processor Interface

1.8V Operation with 3.3V I/O (5V tolerant)

Industrial Operating Temperature Range

control status

ORDERING INFORMATION

PART

DS3105LN

DS3105LN+

TEMP

RANGE

-40 to 85°C

PACKAGE

LQFP64

LQFP64, RoHS compliant

Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement.

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REV: 061507

Preliminary. Subject to Change Without Notice.

DS3105

TABLE OF CONTENTS

STANDARDS COMPLIANCE ............................................................................................................................... 6

APPLICATION EXAMPLE..................................................................................................................................... 7

BLOCK DIAGRAM ................................................................................................................................................ 7

DETAILED DESCRIPTION ................................................................................................................................... 8

DETAILED FEATURES......................................................................................................................................... 9

PIN DESCRIPTIONS .......................................................................................................................................... 11

FUNCTIONAL DESCRIPTION............................................................................................................................ 15

7.1

7.2

7.3

7.4

Overview.................................................................................................................................................... 15

Device Identification and Protection .......................................................................................................... 16

Local Oscillator and Master Clock Configuration ...................................................................................... 16

Input Clock Configuration .......................................................................................................................... 16

7.4.1

7.4.2

7.5

7.5.1

7.5.2

7.5.3

7.6

7.6.1

7.6.2

7.6.3

7.6.4

7.6.5

7.6.6

7.7

7.7.1

7.7.2

7.7.3

7.7.4

7.7.5

7.7.6

7.7.7

7.7.8

7.7.9

Signal Format Configuration......................................................................................................... 16

Frequency Configuration .............................................................................................................. 17

Frequency Monitoring................................................................................................................... 18

Activity Monitoring ........................................................................................................................ 18

Selected Reference Activity Monitoring........................................................................................ 19

Priority Configuration .................................................................................................................... 20

Automatic Selection Algorithm ..................................................................................................... 20

Forced Selection........................................................................................................................... 21

Ultra-Fast Reference Switching.................................................................................................... 21

External Reference Switching Mode ............................................................................................ 21

Output Clock Phase Continuity During Reference Switching....................................................... 21

T0 DPLL State Machine ............................................................................................................... 23

T4 DPLL State Machine ............................................................................................................... 26

Bandwidth..................................................................................................................................... 26

Damping Factor ............................................................................................................................ 26

Phase Detectors ........................................................................................................................... 26

Loss of Phase Lock Detection...................................................................................................... 27

Phase Build-Out ........................................................................................................................... 28

Input to Output (Manual) Phase Adjustment ................................................................................ 28

Phase Recalibration ..................................................................................................................... 28

Input Clock Monitoring............................................................................................................................... 18

Input Clock Priority, Selection and Switching ............................................................................................ 20

DPLL Architecture and Configuration........................................................................................................ 22

7.7.10 Frequency and Phase Measurement ........................................................................................... 29

7.7.11 Input Jitter Tolerance.................................................................................................................... 30

7.7.12 Jitter Transfer ............................................................................................................................... 30

7.7.13 Output Jitter and Wander ............................................................................................................. 30

Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement.

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Preliminary. Subject to Change Without Notice.

7.8

DS3105

Output Clock Configuration ....................................................................................................................... 31

7.8.1

7.8.2

Signal Format Configuration......................................................................................................... 31

Frequency Configuration .............................................................................................................. 31

Sampling....................................................................................................................................... 38

Resampling................................................................................................................................... 39

Enable .......................................................................................................................................... 39

Qualification.................................................................................................................................. 39

Output Clock Alignment................................................................................................................ 39

Frame Sync Monitor ..................................................................................................................... 39

SYNCn Pins.................................................................................................................................. 40

Other Configuration Options......................................................................................................... 40

7.9

Frame and Multiframe Alignment .............................................................................................................. 38

7.9.1

7.9.2

7.9.3

7.9.4

7.9.5

7.9.6

7.9.7

7.9.8

7.10 Microprocessor Interface ........................................................................................................................... 41

7.11 Reset Logic................................................................................................................................................ 43

7.12 Power-Supply Considerations ................................................................................................................... 43

7.13 Initialization................................................................................................................................................ 43

REGISTER DESCRIPTIONS.............................................................................................................................. 44

8.1

8.2

8.3

8.4

9.1

9.2

9.3

9.4

Status Bits ................................................................................................................................................. 44

Configuration Fields................................................................................................................................... 44

Multi-Register Fields.................................................................................................................................. 44

Register Definitions ................................................................................................................................... 45

JTAG Description ...................................................................................................................................... 93

JTAG TAP Controller State Machine Description ..................................................................................... 93

JTAG Instruction Register and Instructions............................................................................................... 95

JTAG Test Registers ................................................................................................................................. 96

JTAG TEST ACCESS PORT AND BOUNDARY SCAN..................................................................................... 93

10 ELECTRICAL CHARACTERISTICS ................................................................................................................... 97

10.1 DC Characteristics..................................................................................................................................... 97

10.2 Input Clock Timing................................................................................................................................... 100

10.3 Output Clock Timing ................................................................................................................................ 100

10.4 SPI Interface Timing ................................................................................................................................ 101

10.5 JTAG Interface Timing............................................................................................................................. 102

10.6 Reset Pin Timing ..................................................................................................................................... 103

11 PIN ASSIGNMENTS ......................................................................................................................................... 104

12 MECHANICAL INFORMATION ........................................................................................................................ 106

13 ACRONYMS AND ABBREVIATIONS............................................................................................................... 108

14 DATA SHEET REVISION HISTORY ................................................................................................................ 109

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Preliminary. Subject to Change Without Notice.

DS3105

LIST OF FIGURES

Figure 2-1. Typical Application Example ..................................................................................................................... 7

Figure 3-1. Functional Block Diagram ......................................................................................................................... 7

Figure 7-1. DPLL Block Diagram ............................................................................................................................... 22

Figure 7-2. T0 DPLL State Transition Diagram ......................................................................................................... 24

Figure 7-3. FSYNC 8 kHz Options............................................................................................................................. 38

Figure 7-4. SPI Clock Phase Options ........................................................................................................................ 42

Figure 7-5. SPI Bus Transactions.............................................................................................................................. 42

Figure 9-1. JTAG Block Diagram............................................................................................................................... 93

Figure 9-2. JTAG TAP Controller State Machine ...................................................................................................... 95

Figure 10-1. Recommended Termination for LVDS Pins .......................................................................................... 99

Figure 10-2. Recommended Termination for LVPECL Signals on Differential Input Pins ........................................ 99

Figure 10-3 Recommended Termination for LVPECL Level-Compatible Output Pins.............................................. 99

Figure 10-4. SPI Interface Timing Diagram ............................................................................................................. 101

Figure 10-5. JTAG Timing Diagram......................................................................................................................... 102

Figure 10-6. Reset Pin Timing Diagram .................................................................................................................. 103

Figure 11-1. Pin Assignment Diagram..................................................................................................................... 105

Figure 12-1. LQFP Mechanical Dimensions............................................................................................................ 106

Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement.

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Preliminary. Subject to Change Without Notice.

DS3105

LIST OF TABLES

Table 1-1. Applicable Telecom Standards................................................................................................................... 6

Table 6-1. Input Clock Pin Descriptions .................................................................................................................... 11

Table 6-2. Output Clock Pin Descriptions.................................................................................................................. 11

Table 6-3. Global Pin Descriptions ............................................................................................................................ 12

Table 6-4. SPI Bus Mode Pin Descriptions ............................................................................................................... 13

Table 6-5. JTAG Interface Pin Descriptions .............................................................................................................. 13

Table 6-6. Power Supply Pin Descriptions ................................................................................................................ 13

Table 7-1. Input Clock Capabilities ............................................................................................................................ 17

Table 7-2. Locking Frequency Modes ....................................................................................................................... 17

Table 7-3. Default Input Clock Priorities .................................................................................................................... 20

Table 7-4. Damping Factors and Peak Jitter/Wander Gain....................................................................................... 26

Table 7-5. T0 DPLL adaptation for the T4 DPLL Phase Measurement Mode .......................................................... 30

Table 7-6. Output Clock Capabilities ......................................................................................................................... 31

Table 7-7. Digital1 Frequencies................................................................................................................................. 32

Table 7-8. Digital2 Frequencies................................................................................................................................. 33

Table 7-9. APLL Frequency to Output Frequencies (T0 APLL and T4 APLL) .......................................................... 33

Table 7-10. T0 APLL Frequency Configuration ......................................................................................................... 33

Table 7-11. T0 APLL2 Frequency Configuration ....................................................................................................... 33

Table 7-12. T4 APLL Frequency Configuration ......................................................................................................... 34

Table 7-13. OC3 and OC6 Output Frequency Selection ........................................................................................... 34

Table 7-14. Possible Frequencies for Programmable Outputs ................................................................................. 35

Table 7-15 T0CR1.T0FREQ Default Settings ........................................................................................................... 37

Table 7-16 T4CR1.T4FREQ Default Settings ........................................................................................................... 37

Table 7-17 OC6 Default Frequency Configuration .................................................................................................... 37

Table 7-18 OC3 Default Frequency Configuration .................................................................................................... 37

Table 7-19. External Frame Sync Source ................................................................................................................. 40

Table 8-1. Register Map ............................................................................................................................................ 45

Table 9-1. JTAG Instruction Codes ........................................................................................................................... 95

Table 9-2. JTAG ID Code .......................................................................................................................................... 96

Table 10-1. Recommended DC Operating Conditions .............................................................................................. 97

Table 10-2. DC Characteristics.................................................................................................................................. 97

Table 10-3. CMOS/TTL Pins ..................................................................................................................................... 98

Table 10-4. LVDS/LVPECL Input Pins ...................................................................................................................... 98

Table 10-5. LVDS Output Pins .................................................................................................................................. 98

Table 10-6. LVPECL Level-Compatible Output Pins................................................................................................. 98

Table 10-7. Input Clock Timing................................................................................................................................ 100

Table 10-8. Input Clock to Output Clock Delay ....................................................................................................... 100

Table 10-9. Output Clock Phase Alignment, Frame Sync Alignment Mode............................................................ 100

Table 10-10. SPI Interface Timing ........................................................................................................................... 101

Table 10-11. JTAG Interface Timing........................................................................................................................ 102

Table 10-12. Reset Pin Timing ................................................................................................................................ 103

Table 11-1. Pin Assignments Sorted by Signal Name............................................................................................. 104

Table 12-1. LQFP Thermal Properties, Natural Convection.................................................................................... 107

Table 12-2. LQFP Theta-JA (θ

) vs. Airflow ........................................................................................................... 107

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DS3105 Related Products

	DS3105	DS3105LN
Description	Line Card Timing IC	Line Card Timing IC

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