531FC771M000DG datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > oscillator> 531FC771M000DG

531FC771M000DG: DescriptionLVDS Output Clock Oscillator, 771MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; Categoryoscillator; File Size215KB，12 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

531FC771M000DG Overview

LVDS Output Clock Oscillator, 771MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

531FC771M000DG Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
Reach Compliance Code	unknown
Other features	TRAY
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	7%
JESD-609 code	e4
Manufacturer's serial number	531
Installation features	SURFACE MOUNT
Nominal operating frequency	771 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	LVDS
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	0.35 ns
Maximum supply voltage	2.75 V
Minimum supply voltage	2.25 V
Nominal supply voltage	2.5 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)
Base Number Matches	1

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

EVISION

R Y S TA L

S C I L L A T O R

(XO)

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH

Networking

SD/HD video

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.1 6/07

Si530/531

Recommended Resources

LOGO! control circuit a

Measurement of voltage, current and power of general frequency converter main circuit

DC, DC single-ended forward converter circuit diagram using UC3828

845ddr computer motherboard circuit diagram_11

Computer motherboard circuit diagram 440BX_32

Computer motherboard circuit diagram 810 1_03

I will comment on solar photovoltaic power generation solutions: I feel that the downloaded information is not specific enough. If there is a specific solution, it is worth discussing. In the current environment of energy shortage, using renewable resources to obta...; 眼大5子 ADI Reference Circuit

Can a mobile phone charger be used as a 5V DC power supply?: Can a mobile phone charger be used as a 5V DC power supply?...; Orima Power technology

SMT reflow oven temperature process curve setting: [align=left][color=rgb(51, 51, 51)][font=-apple-system-font, BlinkMacSystemFont, "][size=17px] With the advancement of science and technology and the improvement of people's living standards, people's...; ohahaha PCB Design

How to configure stm32f103vct6 serial port UART4 and UART5?: [i=s]This post was last edited by Wang Zhao on 2017-2-9 15:09[/i] The asynchronous serial ports UART4 and UART5 of stm32f103vct6 can only send data but not receive data with the following configuratio...; 王zhao stm32/stm8

Help: 51 and 8155 connection problem, analog port method: As the title says, since 8155 only needs the lower eight bits of address, P2 is reserved for other uses, so I want to use common IO to simulate the address bus, ALE, WR and other ports. I wrote the pr...; moon30000 51mcu

LCD Operation: 1602 LCD: 2 rows, 16 dots per row[/b][/color][/size] [size=3][/size] [b][color=#0000ff][/color][/b] [b][color=#0000ff][/color][/b] [b][color=#0000ff]Mainly look at "write instruction" and "write data"...; simonprince MCU

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components