OT PLD, 30ns, CMOS, CDFP24, CERPACK-24
| Parameter Name | Attribute value |
| Maker | Cypress Semiconductor |
| Parts packaging code | DFP |
| package instruction | DFP, |
| Contacts | 24 |
| Reach Compliance Code | unknown |
| ECCN code | 3A001.A.2.C |
| Other features | 10 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK; VARIABLE PRODUCT TERMS |
| maximum clock frequency | 25 MHz |
| JESD-30 code | R-GDFP-F24 |
| JESD-609 code | e0 |
| length | 15.367 mm |
| Dedicated input times | 11 |
| Number of I/O lines | 10 |
| Number of terminals | 24 |
| Maximum operating temperature | 125 °C |
| Minimum operating temperature | -55 °C |
| organize | 11 DEDICATED INPUTS, 10 I/O |
| Output function | MACROCELL |
| Package body material | CERAMIC, GLASS-SEALED |
| encapsulated code | DFP |
| Package shape | RECTANGULAR |
| Package form | FLATPACK |
| Programmable logic type | OT PLD |
| propagation delay | 30 ns |
| Certification status | Not Qualified |
| Maximum seat height | 2.286 mm |
| Maximum supply voltage | 5.5 V |
| Minimum supply voltage | 4.5 V |
| Nominal supply voltage | 5 V |
| surface mount | YES |
| technology | CMOS |
| Temperature level | MILITARY |
| Terminal surface | TIN LEAD |
| Terminal form | FLAT |
| Terminal pitch | 1.27 mm |
| Terminal location | DUAL |
| width | 9.652 mm |
| Base Number Matches | 1 |
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