5962-9215802MXA datasheet, PDF

Datasheet> All Categories > Programmable logic> Programmable logic devices> 5962-9215802MXA

5962-9215802MXA: DescriptionUV PLD, 58ns, 64-Cell, CMOS, CQCC44, WINDOWED, CERAMIC, LCC-44; CategoryProgrammable logic Programmable logic devices; File Size84KB，6 Pages; ManufacturerCypress Semiconductor

Download Datasheet Parametric Compare View All

5962-9215802MXA Overview

UV PLD, 58ns, 64-Cell, CMOS, CQCC44, WINDOWED, CERAMIC, LCC-44

5962-9215802MXA Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Cypress Semiconductor
Parts packaging code	LCC
package instruction	WINDOWED, CERAMIC, LCC-44
Contacts	44
Reach Compliance Code	not_compliant
ECCN code	3A001.A.2.C
Other features	LABS INTERCONNECTED BY PIA; 4 LABS; 64 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK
maximum clock frequency	27 MHz
In-system programmable	NO
JESD-30 code	S-CQCC-J44
JESD-609 code	e0
JTAG BST	NO
length	16.51 mm
Dedicated input times	7
Number of I/O lines	28
Number of macro cells	64
Number of terminals	44
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	7 DEDICATED INPUTS, 28 I/O
Output function	MACROCELL
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	WQCCJ
Encapsulate equivalent code	LDCC44,.7SQ
Package shape	SQUARE
Package form	CHIP CARRIER, WINDOW
Peak Reflow Temperature (Celsius)	225
power supply	5 V
Programmable logic type	UV PLD
propagation delay	58 ns
Certification status	Not Qualified
Filter level	MIL-STD-883
Maximum seat height	4.572 mm
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal surface	Tin/Lead (Sn/Pb) - hot dipped
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	16.51 mm
Base Number Matches	1

Preview

Download Datasheet

View All

EPLD

CY7C340 EPLD Family

Multiple Array Matrix High-Density EPLDs

Features

• Erasable, user-configurable CMOS EPLDs capable of

implementing high-density custom logic functions

• 0.8-micron double-metal CMOS EPROM technology

(CY7C34X)

• Advanced 0.65-micron CMOS technology to increase

performance (CY7C34XB)

• Multiple Array MatriX architecture optimized for speed,

density, and straightforward design implementation

— Programmable Interconnect Array (PIA) simplifies

routing

— Flexible macrocells increase utilization

— Programmable clock control

— Expander product terms implement complex logic

functions

CY7C342B. This allows the designer to replace 50 or more

TTL packages with just one MAX EPLD. The family comes in

a range of densities, shown below. By standardizing on a few

MAX building blocks, the designer can replace hundreds of

different 7400 series part numbers currently used in most dig-

ital systems.

The family is based on an architecture of flexible macrocells

grouped together into Logic Array Blocks (LABs). Within the

LAB is a group of additional product terms called expander

product terms. These expanders are used and shared by the

macrocells, allowing complex functions of up to 35 product

terms to be easily implemented in a single macrocell. A Pro-

grammable Interconnect Array (PIA) globally routes all signals

within devices containing more than one LAB. This architec-

ture is fabricated on the Cypress 0.8-micron, double-lay-

er-metal CMOS EPROM process, yielding devices with signif-

icantly higher integration, density and system clock speed than

the largest of previous generation EPLDs. The CY7C34XB de-

vices are 0.65-micron shrinks of the original 0.8-micron family.

The CY7C34XBs offer faster speed bins for each device in the

Cypress MAX family.

The density and performance of the CY7C340 family is ac-

cessed using Cypress’s

Warp™, Warp

Professional™, or

Warp

Enterprise™ design software.

Warp

provides

state-of-the-art synthesis, fitting, simulation and other devel-

opment tools at a very low cost.

Warp

Professional or

Warp

Enterprise are sophisticated CAE tool that include behavior-

al simulation, graphical waveform editing and more. Consult

the datasheets for

Warp, Warp

Professional and

Warp

Enter-

prise™ for more information about these development tools.

General Description

The Cypress Multiple Array Matrix (MAX®) family of EPLDs

provides a user-configurable, high-density solution to gener-

al-purpose logic integration requirements. With the combina-

tion of innovative architecture and state-of-the-art process, the

MAX EPLDs offer LSI density without sacrificing speed.

The MAX architecture makes it ideal for replacing large

amounts of TTL SSI and MSI logic. For example, a 74161

counter utilizes only 3% of the 128 macrocells available in the

CY7C342B. Similarly, a 74151 8-to-1 multiplexer consumes

less than 1% of the over 1,000 product terms in the

Max Family Members

Feature

Macrocells

MAX Flip-Flops

MAX Latches

[1]

MAX Inputs

[2]

MAX Outputs

Packages

CY7C344(B)

28H,J,W,P

CY7C343(B)

128

44H,J

CY7C342B

128

256

68H,J,R

CY7C346(B)

128

256

84H,J 100R,N

CY7C341B

192

384

84H,J,R

Key: P—Plastic DIP; H—Windowed Ceramic Leaded Chip Carrier; J—Plastic J-Lead Chip Carrier; R—Windowed Pin Grid Array;

W—Windowed Ceramic DIP; N—Plastic Quad Flat Pack

Notes:

1. When all expander product terms are used to implement latches.

2. With one output.

PAL is a registered trademark of Advanced Micro Devices.

MAX is a registered trademark of Altera Corporation.

LASH

370,

Warp, Warp

Professional, and

Warp

Enterprise are trademarks of Cypress Semiconductor Corporation.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

July 19, 2000

5962-9215802MXA Related Products

	5962-9215802MXA	5962-9314401MZC	5962-9314402MUA	5962-9314402MZC	5962-9206202MYC	5962-9314401MUA	5962-9206203MXA	5962-9061102YA	5962-9061102XA
Description	UV PLD, 58ns, 64-Cell, CMOS, CQCC44, WINDOWED, CERAMIC, LCC-44	UV PLD, 75ns, 128-Cell, CMOS, CPGA100, WINDOWED, CERAMIC, PGA-100	UV PLD, 59ns, 128-Cell, CMOS, CQCC84, WINDOWED, CERAMIC, LCC-84	UV PLD, 59ns, 128-Cell, CMOS, CPGA100, WINDOWED, CERAMIC, PGA-100	UV PLD, 45ns, 192-Cell, CMOS, CPGA84,	UV PLD, 75ns, 128-Cell, CMOS, CQCC84, WINDOWED, CERAMIC, LCC-84	UV PLD, 75ns, 192-Cell, CMOS, CQCC84, WINDOWED, CERAMIC, LCC-84	UV PLD, 40ns, PAL-Type, CMOS, CQCC28, WINDOWED, CERAMIC, LCC-28	UV PLD, 40ns, PAL-Type, CMOS, CDIP28, 0.300 INCH, WINDOWED, CERDIP-28
Maker	Cypress Semiconductor	Cypress Semiconductor	Cypress Semiconductor	Cypress Semiconductor	Cypress Semiconductor	Cypress Semiconductor	Cypress Semiconductor	Cypress Semiconductor	Cypress Semiconductor
package instruction	WINDOWED, CERAMIC, LCC-44	WPGA, PGA100M,13X13	WINDOWED, CERAMIC, LCC-84	WPGA, PGA100M,13X13	WPGA, PGA84M,11X11	WINDOWED, CERAMIC, LCC-84	WQCCJ, LDCC84,1.2SQ	WINDOWED, CERAMIC, LCC-28	0.300 INCH, WINDOWED, CERDIP-28
Reach Compliance Code	not_compliant	unknown	not_compliant	unknown	unknown	not_compliant	unknown	not_compliant	not_compliant
ECCN code	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C
Other features	LABS INTERCONNECTED BY PIA; 4 LABS; 64 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK	LABS INTERCONNECTED BY PIA; 8 LABS; 128 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK	LABS INTERCONNECTED BY PIA; 8 LABS; 128 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK	LABS INTERCONNECTED BY PIA; 8 LABS; 128 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK	LABS INTERCONNECTED BY PIA; 12 LABS; 192 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK	LABS INTERCONNECTED BY PIA; 8 LABS; 128 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK	LABS INTERCONNECTED BY PIA; 12 LABS; 192 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK	MACROCELLS INTERCONNECTED BY PIA; 32 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK	MACROCELLS INTERCONNECTED BY PIA; 32 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK
maximum clock frequency	27 MHz	22.2 MHz	27.7 MHz	27.7 MHz	40 MHz	22.2 MHz	22.2 MHz	27 MHz	27 MHz
JESD-30 code	S-CQCC-J44	S-CPGA-P100	S-CQCC-J84	S-CPGA-P100	S-CPGA-P84	S-CQCC-J84	S-CQCC-J84	S-CQCC-J28	R-GDIP-T28
JESD-609 code	e0	e4	e0	e4	e4	e0	e0	e0	e0
length	16.51 mm	33.3375 mm	29.21 mm	33.3375 mm	27.94 mm	29.21 mm	29.21 mm	11.43 mm	37.0205 mm
Dedicated input times	7	19	19	19	7	19	7	7	7
Number of I/O lines	28	64	48	64	64	48	64	16	16
Number of terminals	44	100	84	100	84	84	84	28	28
Maximum operating temperature	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C
Minimum operating temperature	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C
organize	7 DEDICATED INPUTS, 28 I/O	19 DEDICATED INPUTS, 64 I/O	19 DEDICATED INPUTS, 48 I/O	19 DEDICATED INPUTS, 64 I/O	7 DEDICATED INPUTS, 64 I/O	19 DEDICATED INPUTS, 48 I/O	7 DEDICATED INPUTS, 64 I/O	7 DEDICATED INPUTS, 16 I/O	7 DEDICATED INPUTS, 16 I/O
Output function	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL
Package body material	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, GLASS-SEALED
encapsulated code	WQCCJ	WPGA	WQCCJ	WPGA	WPGA	WQCCJ	WQCCJ	WQCCJ	WDIP
Encapsulate equivalent code	LDCC44,.7SQ	PGA100M,13X13	LDCC84,1.2SQ	PGA100M,13X13	PGA84M,11X11	LDCC84,1.2SQ	LDCC84,1.2SQ	LDCC28,.5SQ	DIP28,.3
Package shape	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	RECTANGULAR
Package form	CHIP CARRIER, WINDOW	GRID ARRAY, WINDOW	CHIP CARRIER, WINDOW	GRID ARRAY, WINDOW	GRID ARRAY, WINDOW	CHIP CARRIER, WINDOW	CHIP CARRIER, WINDOW	CHIP CARRIER, WINDOW	IN-LINE, WINDOW
power supply	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V
Programmable logic type	UV PLD	UV PLD	UV PLD	UV PLD	UV PLD	UV PLD	UV PLD	UV PLD	UV PLD
propagation delay	58 ns	75 ns	59 ns	59 ns	45 ns	75 ns	75 ns	40 ns	40 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Filter level	MIL-STD-883	MIL-STD-883	MIL-STD-883	MIL-STD-883	38535Q/M;38534H;883B	MIL-STD-883	MIL-STD-883	38535Q/M;38534H;883B	38535Q/M;38534H;883B
Maximum seat height	4.572 mm	5.207 mm	5.08 mm	5.207 mm	3.81 mm	5.08 mm	5.08 mm	4.572 mm	5.08 mm
Maximum supply voltage	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V
Minimum supply voltage	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V
Nominal supply voltage	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V
surface mount	YES	NO	YES	NO	NO	YES	YES	YES	NO
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY
Terminal surface	Tin/Lead (Sn/Pb) - hot dipped	GOLD	Tin/Lead (Sn/Pb) - hot dipped	GOLD	GOLD	Tin/Lead (Sn/Pb) - hot dipped	TIN LEAD	Tin/Lead (Sn/Pb) - hot dipped	Tin/Lead (Sn/Pb) - hot dipped
Terminal form	J BEND	PIN/PEG	J BEND	PIN/PEG	PIN/PEG	J BEND	J BEND	J BEND	THROUGH-HOLE
Terminal pitch	1.27 mm	2.54 mm	1.27 mm	2.54 mm	2.54 mm	1.27 mm	1.27 mm	1.27 mm	2.54 mm
Terminal location	QUAD	PERPENDICULAR	QUAD	PERPENDICULAR	PERPENDICULAR	QUAD	QUAD	QUAD	DUAL
width	16.51 mm	33.3375 mm	29.21 mm	33.3375 mm	27.94 mm	29.21 mm	29.21 mm	11.43 mm	7.62 mm
Base Number Matches	1	1	1	1	1	1	1	1	1
Is it Rohs certified?	incompatible	-	incompatible	-	-	incompatible	-	incompatible	incompatible
Parts packaging code	LCC	PGA	LCC	PGA	-	LCC	LCC	QLCC	DIP
Contacts	44	100	84	100	-	84	84	28	28
In-system programmable	NO	NO	NO	NO	NO	NO	NO	-	-
JTAG BST	NO	NO	NO	NO	NO	NO	NO	-	-
Number of macro cells	64	128	128	128	192	128	192	-	-
Peak Reflow Temperature (Celsius)	225	-	NOT SPECIFIED	-	-	NOT SPECIFIED	-	225	NOT SPECIFIED
Maximum time at peak reflow temperature	30	-	NOT SPECIFIED	-	-	NOT SPECIFIED	-	30	NOT SPECIFIED

Recommended Resources

Even-numbered voltage doubler full-wave rectifier circuit a

Controllable integrator (F007) circuit diagram

Shuanglu brand BD-100 refrigerator circuit

Wireless dual-tone electronic doorbell circuit diagram

Long delay constant current charging circuit circuit diagram

±5～25V bipolar regulated power supply circuit

Help, the program under FR5969 shows unknown device: I have just got the MSP-EXP430FR5969 launch pad. After connecting it to the computer via USB, it shows that the device is connected normally. However, when I select FR5969 in CCS5.5 to download the pr...; deer326 Microcontroller MCU

MSP430 printf implementation: I used IAR to debug the ADXL345 program of MSP430 and found that after successfully reading ADXL345, there was always a problem with the printf output. ;i++) printf("%d ",buf[i]); printf(""); The outp...; 568760310 Microcontroller MCU

Equipment to be purchased: Handheld device with POCKET PC or MOBILE operating system and WIFI wireless communication: Other technical requirements: No price, within 1000 yuan...; hyf9290 Embedded System

Launchpad development in Ubuntu: The software installation method in launchpad development on ubuntu11.10 may be different from the actual one, but as long as it is installed correctly, it will definitely work....; monkhooder Microcontroller MCU

stm3210B development board smart card: I am using the stm3210B development board to do a smart card experiment. When using the smartcard demo program that comes with the development board, after inserting the card, the sw1 read back is 0x6...; axlylee stm32/stm8

CC2530 Development Kit PCB Schematic: CC2530 Development Kit PCB Schematic...; 1456999234@qq.c RF/Wirelessly

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components