PRELIMINARY DATASHEET
PLL CLOCK MULTIPLIER
Description
The IDT5P40041 is the most cost effective way to generate
a high-quality, high-frequency clock output from a lower
frequency crystal or clock input. Using Phase-Locked Loop
(PLL) techniques, the device uses a standard fundamental
mode, inexpensive crystal or clock input to produce output
clocks up to 200 MHz.
Stored in the chip’s ROM is the ability to generate nine
different multiplication factors, allowing one chip to output
many common frequencies (see table on page 2).
The device also has an output enable pin which tri-states
the clock output when the OE pin is taken low.
This product is intended for clock generation. It has low
output jitter (variation in the output period), but input to
output skew and jitter are not defined or guaranteed.
IDT5P40041
Features
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Packaged as 8-pin SOIC, MSOP, or DFN
RoHS 6 (green and lead free) compliant packaging
Input crystal or clock frequency of 6.25 - 27 MHz
Output clock frequencies up to 200 MHz
Extremely low jitter of 25 ps (one sigma)
Duty cycle of 45/55 up to 200 MHz
Frequency multiplication of 5x, 6x, 10x and 12x
Operating voltage of 1.5 V to 1.8 V
Tri-state output for board level testing
Ideal for oscillator replacement
Advanced, low-power CMOS process
Industrial Temperature Range: -40 to +85° C
Block Diagram
VDD
S1:0
X1/ICLK
Crystal or
Clock input
X2
2
Crystal
Oscillator
PLL Clock
Multiplier
Circuitry
and ROM
CLK
Optional crystal capacitors
GND
OE
IDT™
PLL CLOCK MULTIPLIER
1
IDT5P40041
REV D 031908
IDT5P40041
PLL CLOCK MULTIPLIER
CLOCK MULTIPLIER
Pin Assignment
X1/ I CLK
VDD
GND
S1
1
2
3
4
8
7
6
5
X2
OE
S0
CLK
8 Pi n ( 150 mi l ) SOI C
Clock Output Table
1.5 V Operation
S1 S0
0
0
1
1
0
1
0
1
CLK
5X input
6X input
10X input
12X input
Min Input
(MHz)
6.25
7
6.25
5.2
Max Input
(MHz)
20
22
20
16.667
1.8 V Operation
Min Input
(MHz)
6.25
7
6.25
5.2
Max Input
(MHz)
25
27
25
20.833
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
Pin
Name
XI/ICLK
VDD
GND
S1
CLK
S0
OE
X2
Pin
Type
Input
Power
Power
Input
Output
Input
Input
Output
Pin Description
Crystal connection or clock input.
Connect to +1.5 V to +1.8 V.
Connect to ground.
Select 1 for output clock. Connect to GND or VDD.
Clock output per table above.
Select 0 for output clock. Connect to GND or VDD.
Output enable. Tri-states CLK output when low. Internal pull-up.
Crystal connection. Leave unconnected for clock input.
IDT™
PLL CLOCK MULTIPLIER
2
IDT5P40041
REV D 031908
IDT5P40041
PLL CLOCK MULTIPLIER
CLOCK MULTIPLIER
External Components
Decoupling Capacitor
As with any high-performance mixed-signal IC, the
IDT5P40041 must be isolated from system power supply
noise to perform optimally.
A decoupling capacitor of 0.01µF must be connected
between VDD and the GND. It must be connected close to
the device to minimize lead inductance. No external power
supply filtering is required for the IDT5P40041.
Crystal Load Capacitors
The total on-chip capacitance is approximately 12 pF. A
parallel resonant, fundamental mode crystal should be
used. The device crystal connections should include pads
for small capacitors from X1 to ground and from X2 to
ground. These capacitors are used to adjust the stray
capacitance of the board to match the nominally required
crystal load capacitance. Because load capacitance can
only be increased in this trimming process, it is important to
keep stray capacitance to a minimum by using very short
PCB traces (and no vias) between the crystal and device.
Crystal capacitors, if needed, must be connected from each
of the pins X1 and X2 to ground.
The value (in pF) of these crystal caps should equal (C
L
-12
pF)*2. In this equation, C
L
= crystal load capacitance in pF.
Example: For a crystal with a 16 pF load capacitance, each
crystal capacitor would be 8 pF [(16-12) x 2 = 8].
Series Termination Resistor
A 33Ω terminating resistor can be used next to the CLK pin
for trace lengths over one inch.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the IDT5P40041. These ratings, which
are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at
these or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature
Storage Temperature
Soldering Temperature
5V
Rating
-0.5 V to VDD+0.5 V
0 to +70° C
-65 to +150° C
260° C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature (commercial)
Power Supply Voltage (measured in respect to GND)
Min.
0
+1.425
Typ.
Max.
+70
+1.89
Units
°
C
V
IDT™
PLL CLOCK MULTIPLIER
3
IDT5P40041
REV D 031908
IDT5P40041
PLL CLOCK MULTIPLIER
CLOCK MULTIPLIER
DC Electrical Characteristics
VDD=1.5 V ±
5%,
Ambient temperature -40 to +85° C, unless stated otherwise
Parameter
Operating Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Operating Supply Current
Nominal Output Impedance
On-Chip Pull-up Resistor
Input Capacitance
Short Circuit Current
Symbol
VDD
V
IH
V
IL
V
OH
V
OL
IDD
Z
O
Conditions
ICLK, OE, S0, S1.
Note 1
I
OH
= -6 mA
I
OL
= 6 mA
No load, 100 MHz
Pin 7
Min.
1.425
0.65VDD
0.75VDD
Typ.
Max.
1.575
VDD+0.3
0.35VDD
0.25VDD
Units
V
V
V
V
V
mA
Ω
kΩ
pF
mA
TBD
20
270
5
±28
C
IN
I
OS
ICLK, OE, S0, S1
Notes: 1. Nominal switching threshold is VDD/2
VDD=1.8 V ±5%,
Ambient temperature -40 to +85° C, unless stated otherwise
Parameter
Operating Voltage
Input High Voltage, ICLK
Input Low Voltage, ICLK
Output High Voltage
Output Low Voltage
Operating Supply Current
Nominal Output Impedance
On-Chip Pull-up Resistor
Input Capacitance
Short Circuit Current
Symbol
VDD
V
IH
V
IL
V
OH
V
OL
IDD
Z
O
Conditions
ICLK, OE, S0, S1.
Note 1
I
OH
= -8 mA
I
OL
= 8 mA
No load, 100 MHz
Pin 7
Min.
1.71
0.65VDD
1.35
Typ.
Max.
1.89
VDD+0.3
0.35VDD
0.45
Units
V
V
V
V
V
mA
Ω
kΩ
pF
mA
TBD
20
270
5
±50
C
IN
I
OS
ICLK, OE, S0, S1
Notes: 1. Nominal switching threshold is VDD/2
IDT™
PLL CLOCK MULTIPLIER
4
IDT5P40041
REV D 031908
IDT5P40041
PLL CLOCK MULTIPLIER
CLOCK MULTIPLIER
AC Electrical Characteristics
VDD = 1.5 V ±5%,
Ambient Temperature -40 to +85° C, unless stated otherwise
Parameter
Input Frequency
Output Rise Time
Output Fall Time
Output Clock Duty Cycle
Output Enable Time, OE high to
output on
Absolute Clock Period Jitter
One Sigma Clock Period Jitter
Symbol
F
IN
t
OR
t
OF
t
OD
Conditions
20% to 80%, Note 3
80% to 20%, Note 3
Min.
Typ.
see pg.2
1.0
1.0
Max. Units
MHz
ns
ns
55
%
ns
ps
ps
45
49-51
50
t
ja
t
js
Deviation from mean
+70
25
VDD = 1.8 V ±5%,
Ambient Temperature -40 to +85° C, unless stated otherwise
Parameter
Input Frequency
Output Rise Time
Output Fall Time
Output Clock Duty Cycle
Output Enable Time, OE high to
output on
Absolute Clock Period Jitter
One Sigma Clock Period Jitter
Symbol
F
IN
t
OR
t
OF
t
OD
Conditions
20% to 80%, Note 3
80% to 20%, Note 3
Min.
Typ.
see pg. 2
1.0
1.0
Max. Units
MHz
ns
ns
55
%
ns
ps
ps
45
49-51
50
t
ja
t
js
Deviation from mean
+70
25
Notes: 1. With rail to rail input clock
2. Between any 2 outputs with equal loading.
3. Measured with a 5 pF load.
IDT™
PLL CLOCK MULTIPLIER
5
IDT5P40041
REV D 031908
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