Agilent HCTL-2032, HCTL-2032-SC,
HCTL-2022
Quadrature Decoder/Counter
Interface ICs
Data Sheet
Features
• Interfaces Encoder to
Microprocessor
• 33 MHz Clock Operation
• Programmable Count Modes (1x,
2x or 4x)
• Single or Dual Axis Support
• Index Channel Support
Description
The HCTL- 20XX- XX is CMOS
ICs that perform the
quadrature decoder, counter,
and bus interface function. The
HCTL- 20XX- XX is designed to
improve system performance in
digital closed loop motion
control systems and digital data
input systems. It does this by
shifting time intensive
quadrature decoder functions to
a cost effective hardware
solution. The HCTL- 20XX- XX
consists of a quadrature
decoder logic, a binary up/
down state counter, and an 8-
bit bus interface. The use of
Schmitt- triggered CMOS inputs
and input noise filters allows
reliable operation in noisy
environments. The HCTL- 20XX-
XX contains 32- bit counter and
provides LSTLL compatible tri-
state output buffers. Operation
is specified for a temperature
range from
−40
to +100°C at
clock frequencies up to 33MHz.
The HCTL- 2032 and HCTL-
2032- SC have dual- axis
capability and index channel
support. Both devices can be
programmed as 4x/2x/1x count
mode. The HCTL- 2032 and
HCTL2032- SC also provides
quadrature decoder output
signals and cascade signals for
use with many standard
computer ICs.
The HCTL- 2022 has most of the
HCTL- 2032 features, but it can
only supports single axis and
fixed at 4x count mode. The
HCTL- 2022 doesn’t provide
decoder output and cascade
signals.
• High Noise Immunity:
• Schmitt Trigger Inputs and Digital
Noise Filter
• 32-Bit Binary Up/Down Counter
• Latched Outputs
• 8-Bit Tristate Interface
• 8, 16, 24, or 32-Bit Operating Modes
• Quadrature Decoder Output
Signals, Up/Down and Count
• Cascade Output Signals, Up/Down
and Count
• Substantially Reduced System
Software
•
5V Operation (V
DD
−
V
SS
)
• TTL/CMOS Compatible I/O
•
Operating Temperature: -40°C to
100°C
• 32-Pin PDIP, 32-Pin SOIC, 20-Pin
PDIP
Applications
• Interface Quadrature Incremental
Encoders to Microprocessors
• Interface Digital Potentiometers to
Digital Data Input Buses
ESD WARNING:
Standard CMOS handling precautions should be observed with the HCTL- 2032 family ICs.
Operating Characteristics
Table 1. Absolute Maximum Ratings
(All voltages below are referenced to V
SS
)
Parameter
DC Supply Voltage
Input Voltage
Storage Temperature
Operating Temperature [1]
Table 2. Recommended Operating Conditions
Parameter
DC Supply Voltage
Ambient Temperature [1]
Symbol
V
DD
V
IN
T
S
T
A
Symbol
V
DD
T
A
Limits
-0.3 to +6.0
-0.3 to (V
DD
+0.3)
-55 to +150
-40 to +100
Units
V
V
°C
°C
Limits
4.5 to 5.5
-40 to +100
Units
V
°C
Table 3. DC Characteristics V
DD
= 5V
±
5%; T
A
= -40 to 100°C
Symbol
Parameter
Condition
V
IL [2]
V
IH [2]
V
T+
V
T-
V
H
I
IN
V
OH [2]
V
OL [2]
I
OZ
I
DD
C
IN [3]
C
OUT [3]
Low-Level Input Voltage
High-Level Input Voltage
Schmitt-Trigger Positive-Going Threshold
Schmitt-Trigger Negative-Going Threshold
Schmitt-Trigger Hysteresis
Input Current
High-Level Output Voltage
Low-Level Output Voltage
High-Z Output Leakage Current
Quiescent Supply Current
Input Capacitance
Output Capacitance
V
IN
=V
SS
or V
DD
I
OH
= -3.75 mA
I
OL
= +3.75mA
V
O
=V
SS
or V
DD
V
IN
=Vss or V
DD
Any Input
Any Output
Min
3.5
Typ
Max
1.5
Unit
V
V
V
V
V
3.5
1.0
1.0
-10
2.4
-10
1.5
2.0
1
4.5
0.2
1
1
5
5
4.0
+10
0.4
+10
10
µA
V
V
µA
µA
pF
pF
Notes
1. Free Air
2. In general, for any V
DD
between the allowable limits (+4.5V to +5.5V), V
IL
= 0.3V
DD
and
V
IH
= 0.7V
DD
; typical values are V
OH
= V
DD
−
0.5V and V
OL
= V
SS
+ 0.2V
3. Including package capacitance
4
Functional Pin Description
Table 4. Functional Pin Descriptions.
Pin
Symbol
HCTL
2032/
2032-SC
1
18
5
15
16
14
13
17
19
12
11
HCTL
2022
1
12
3
10
NC
9
NC
11
NC
8
NC
Description
V
DD
V
SS
CLK
CHA
X
CHA
Y
CHB
X
CHB
Y
CHI
X
CHI
Y
RSTNX
RSTNY
Power Supply
Ground
CLK is a Schmitt-trigger input for the external clock signal.
CHA
X
, CHA
Y
, CHB
X
, and CHB
Y
are Schmitt-trigger inputs that accept the outputs from
a quadrature-encoded source, such as incremental optical shaft encoder. Two
channels, A and B, nominally 90 degrees out of phase, are required. CHA
X
and CHB
X
are the 1
st
axis and CHA
Y
and CHB
Y
are the 2
nd
axis.
CHI
X
and CHI
Y
are Schmitt-trigger inputs that accept the outputs of Index channel
from an incremental optical shaft encoder.
This active low Schmitt-trigger input clears the internal position counter and the
position latch. It also resets the inhibit logic. RST
X
/ and RST
Y
/ are asynchronous with
respect to any other input signals. RST
X
/ is to reset the 1
st
axis counter and RST
Y
/ is
to reset the 2
nd
axis counter.
This CMOS active low input enables the tri-state output buffers. The OE/, SEL1, and
SEL2 inputs are sampled by the internal inhibit logic on the falling edge of the clock to
control the loading of the internal position data latch.
These CMOS inputs directly controls which data byte from the position latch is
enabled into the 8-bit tri-state output buffer. As in OE/ above, SEL
1
and SEL
2
also
control the internal inhibit logic.
OEN
7
5
SEL1
SEL2
6
26
4
17
SEL1
0
1
0
1
EN1
EN2
2
3
NC
NC
SEL2
1
1
0
0
MSB
D4
BYTE SELECTED
2ND
3RD
D3
D2
LSB
D1
These CMOS control pins are set to high or low to activate the selected count mode
before the decoding begins.
EN1
0
1
0
1
EN2
0
0
1
1
4x
On
On
On
Count Modes
2x
Illegal Mode
1x
X/Y
CNTDEC
X
CNTDEC
Y
U/Dx
U/Dy
32
27
28
8
9
NC
NC
NC
6
NC
Select the 1
st
or 2
nd
axis data to be read. Low bit enables the 1
st
axis data, while high
bit enables the 2
nd
axis data.
A pulse is presented on this LSTTL-compatible output when the quadrature decoder
(4x/2x/1x) has detected a state transition. CNTDEC
X
is for 1
st
axis and CNTDEC
Y
is
for 2
nd
axis.
This LSTTL-compatible output allows the user to determine whether the IC is
counting up or down and is intended to be used with the CNTDEC and CNTCAS
outputs. The proper signal U (high level) or D/ (low level) will be present before the
rising edge of the CNTDEC and CNTCAS outputs.
5
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