DATASHEET
LOW PHASE NOISE T1/E1 CLOCK GENERATOR
Description
The MK1581-01 provides synchronization and timing
control for T1 and E1 based network access or multitrunk
telecommunication systems. The device accepts an 8 kHz
frame clock input and uses an on-chip VCXO to produce a
synchronized low phase noise clock output.
This monolithic IC, combined with an external inexpensive
quartz crystal, can be used to replace a more costly hybrid
VCXO retiming module. Through selection of external loop
filter components values, the device can be tailored to meet
the system’s clock jitter attenuation requirements. Low-pass
jitter attenuation characteristics in the Hz range are
possible.
MK1581-01
Features
•
Generates a T1 (1.544 MHz) or E1 (2.048 MHz) output
•
•
•
•
•
•
•
•
clock from an 8kHz frame clock input
Configurable jitter attenuation characteristics, excellent
for use as a Stratum source de-jitter circuit
VCXO-based clock generation ensures very low jitter and
phase noise generation
Output clock is phase and frequency locked to the input
reference clock
+115ppm minimum crystal frequency pullability range,
using recommended crystal
Industrial temperature range
Low power CMOS technology
16 pin TSSOP package
Single 3.3 V power supply
Block Diagram
R
SET
Pullable Crystal
X1
X2
VDD
VDD
3
ISET
Phase
Detector
8kHz_IN
Charge
Pump
VCXO
Output
Divider
CLK
Feedback
Divider
SEL
CHGP
R
S
C
S
VIN
GND
5
C
P
IDT™
LOW PHASE NOISE T1/E1 CLOCK GENERATOR
1
MK1581-01
REV F 051310
MK1581-01
LOW PHASE NOISE T1/E1 CLOCK GENERATOR
VCXO AND SYNTHESIZER
Pin Assignment
VDD
VDD
VDD
VIN
GND
GND
GND
CHGP
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
X1
X2
8kHz_IN
SEL
CLK
GND
GND
ISET
Output Clock Selection Table
Input
Clock
8 kHz
8 kHz
SEL
0
1
Output
Clock
(MHz)
1.544
2.048
Crystal
Used (MHz)
24.704
24.576
16 pin 4.40 mil body, 0.65 mm pitch TSSOP
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin
Name
VDD
VDD
VDD
VIN
GND
GND
GND
CHGP
ISET
GND
GND
CLK
SEL
8kHz_IN
X2
X1
Pin
Type
Power
Power
Power
Input
Power
Power
Power
Output
–
Power
Power
Output
Input
Input
–
–
Pin Description
Power Supply. Connect to +3.3 V.
Power Supply. Connect to +3.3 V.
Power Supply. Connect to +3.3 V.
VCXO Control Voltage Input. Connect this pin to CHGP pin and the external loop
filter as shown in this data sheet.
Connect to ground.
Connect to ground.
Connect to ground.
Charge Pump Output. Connect this pin to the external loop filter and to pin VIN.
Charge pump current setting node, connection for setting resistor.
Connect to ground.
Connect to ground.
Clock Output.
Output Frequency Selection. Determines output frequency as per table above.
Internal pull-up.
8 kHz reference clock input.
Crystal Output. Connect this pin to the specified crystal.
Crystal Input. Connect this pin to the specified crystal.
IDT™
LOW PHASE NOISE T1/E1 CLOCK GENERATOR
2
MK1581-01
REV F 051310
MK1581-01
LOW PHASE NOISE T1/E1 CLOCK GENERATOR
VCXO AND SYNTHESIZER
Functional Description
The MK1581-01 is a clock generator IC that generates a T1
or E1 reference clock directly from an internal VCXO circuit
that works in conjunction with an external quartz crystal.
The VCXO output frequency and phase is controlled by an
internal PLL (Phase Locked Loop) circuit, enabling the
device to perform clock regeneration from an 8 kHz input
reference clock.
Most typical PLL clock devices use an internal VCO (Voltage
Controlled Oscillator) for output clock generation. By using
a VCXO with an external crystal, the MK1581-01 is able to
generate a low jitter, low phase-noise output clock. The low
bandwidth capability of the PLL circuit serves to provide
input clock jitter attenuation and enables stable operation
with the low frequency input reference clock.
The internal VCXO circuit requires an external pullable
crystal for operation. External loop filter components enable
a PLL configuration with low loop bandwidth.
The frequency of oscillation of a quartz crystal is determined
by its cut and by the external load capacitance. The
MK1581-01 incorporates variable load capacitors on-chip
which “pull”, or change, the frequency of the crystal. The
crystals specified for use with the MK1581-01 are designed
to have zero frequency error when the total of on-chip +
stray capacitance is 14 pF. To achieve this, the layout should
use short traces between the MK1581-01 and the crystal.
A complete description of the recommended crystal
parameters is in application note MAN05.
A list of approved crystals is located on the IDT web site
(www.idt.com).
PLL Loop Filter Components
A phased-locked loop (PLL) is a control system that keeps
the VCO frequency and phase locked with the input
reference clock. Like all control systems, analog PLL circuits
use a loop filter to establish operating stability. The
MK1581-01 uses external loop filter components for the
following reasons:
1) Larger loop filter capacitor values can be used, allowing
a lower loop bandwidth. This enables the use of lower input
clock reference frequencies and also input clock jitter
attenuation capabilities. Larger loop filter capacitors also
allow higher loop damping factors when less passband
peaking is desired.
2) The loop filter values can be user selected to optimize
loop response characteristics for a given application.
Referencing the External Component Schematic on this
page, the external loop filter is made up of components R
S
,
C
S
and C
P
. R
SET
establishes PLL charge pump current and
therefore influences loop filter characteristics.
Design aid tools for configuring the loop filter can be found
at www.idt.com, including on-line and PC-based calculators.
Application Information
Output Frequency Configuration
The MK1581-01 is configured to generate either a 1.544
MHz T1 clock or a 2.048 MHz E1 clock from an 8 kHz input
clock. Please refer to the Output Clock Selection Table on
Page 2. Input bit SEL is set according to this table, as is the
external crystal frequency. Please refer to the Quartz
Crystal section on this page regarding external crystal
requirements.
Quartz Crystal
It is important that the correct type of quartz crystal is used
with the MK1581-01. Failure to do so may result in reduced
frequency pullability range, inability of the loop to lock, or
excessive output phase jitter.
The MK1581-01 operates by phase-locking the VCXO
circuit to the input signal of the selected ICLK input. The
VCXO consists of the external crystal and the integrated
VCXO oscillator circuit. To achieve the best performance
and reliability, a crystal device with the recommended
parameters (shown below) must be used, and the layout
guidelines discussed in the PCB Layout Recommendations
section must be followed.
IDT™
LOW PHASE NOISE T1/E1 CLOCK GENERATOR
3
MK1581-01
REV F 051310
MK1581-01
LOW PHASE NOISE T1/E1 CLOCK GENERATOR
VCXO AND SYNTHESIZER
External Component Schematic
Refer to Crystal Tuning section
C
L
C
L
C
P
VDD
VDD
VDD
VIN
GND
R
S
GND
GND
C
S
CHGP
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
X1
X2
8kHz_IN
SEL
CLK
GND
GND
ISET
Pullable
Crystal
R
SET
Recommended Loop Filter Values Vs. Output Frequency Selection
Crystal
SEL Output Freq Multiplier
(N)
0
1
1.544 MHz
2.048 MHz
3088
3072
R
SET
120 kΩ
120 kΩ
R
S
1.0 MΩ
1.0 MΩ
C
S
0.1
µF
0.1
µF
C
P
4.7 nF
4.7 nF
Loop
Bandwidth
(-3dB point)
Damping
Factor
1.4
1.4
18 Hz
19 Hz
IDT™
LOW PHASE NOISE T1/E1 CLOCK GENERATOR
4
MK1581-01
REV F 051310
MK1581-01
LOW PHASE NOISE T1/E1 CLOCK GENERATOR
VCXO AND SYNTHESIZER
A “normalized” PLL loop bandwidth may be calculated as
follows:
Charge Pump Current Table
R
S
×
I
CP
×
575
NBW
= -----------------------------------------
N
R
SET
1.4 MΩ
680 kΩ
540 kΩ
120 kΩ
Charge Pump Current
(I
CP
)
10
µA
20
µA
25
µA
100
µA
The “normalized” bandwidth (NBW) equation above does
not take into account the effects of damping factor or the
second pole. NBW is approximately equal to the actual -3dB
bandwidth of the loop when the damping factor is about 5
and C
2
is very small. In most applications, NBW is about
75% of the actual -3dB bandwidth. However, NBW does
provide a useful approximation of filter performance.
The loop damping factor is calculated as follows:
Special considerations must be made in choosing loop
components C
S
and C
P
.
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50Ω trace (a commonly
used trace impedance), place a 33Ω resistor in series with
the clock line, as close to the clock output pin as possible.
The nominal impedance of the clock output is 20Ω (The
.
optional series termination resistor is not shown in the
External Component Schematic.)
Damping Factor = R
S
×
625
×
I
CP
×
C
S
------------------------------------------
-
N
Where:
R
S
= Value of resistor in loop filter (Ohms)
I
CP
= Charge pump current (amps)
(refer to Charge Pump Current Table, below)
N = Crystal multiplier shown in the above table
C
S
= Value of capacitor C
S
in loop filter (Farads)
As a general rule, the following relationship should be
maintained between components C
S
and C
P
in the loop
filter:
Decoupling Capacitors
As with any high performance mixed-signal IC, the
MK1581-01 must be isolated from system power supply
noise to perform optimally.
Decoupling capacitors of 0.01µF must be connected
between each VDD and the PCB ground plane. To further
guard against interfering system supply noise, the
MK1581-01 should use one common connection to the PCB
power plane as shown in the diagram on the next page. The
ferrite bead and bulk capacitor help reduce lower frequency
noise in the supply that can lead to output clock phase
modulation.
C
P
S
=
-----
-
C
20
IDT™
LOW PHASE NOISE T1/E1 CLOCK GENERATOR
5
MK1581-01
REV F 051310
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