24-Lane 3-Port PCI Express®
Switch
89PES24N3
Product Brief
Device Overview
The 89HPES24N3 is a member of IDT’s PRECISE™ family of PCI
Express® bridging and switching solutions offering the next-generation
I/O interconnect standard. The PES24N3 is a 24-lane, 3-port peripheral
chip that performs PCI Express Base switching with a feature set opti-
mized for high performance applications such as servers, storage, and
communications/networking. It provides high-performance I/O connec-
tivity and switching functions between a PCI Express upstream port and
two downstream ports or peer-to-peer switching between downstream
ports.
x
x
x
round robin algorithms
Static lane reversal on all ports
Polarity inversion
Ability to load device configuration from serial EEPROM
Legacy Support
x
PCI compatible INTx emulation
x
Bus locking
Highly Integrated Solution
x
Integrates 24 2.5 Gbps embedded SerDes, 8B/10B encoder/
decoder (no separate transceivers needed)
x
Incorporates on-chip internal memory for packet buffering
and queueing
x
Requires no external components
Reliability, Availability, and Serviceability (RAS)
Features
x
Internal end-to-end parity protection on all TLPs ensures
data integrity even in systems that do not implement end-to-
end CRC (ECRC)
x
ECRC passed through
x
Supports PCI Express Native Hot-Plug
– Compatible with Hot-Plug I/O expanders used on PC mother-
boards
x
Hot-Swap capable I/O
Features
eatures
High Performance PCI Express Switch
x
24 PCI Express lanes (2.5Gbps), 3 switch ports
x
12 GBps (96 Gbps) aggregate switching throughput
x
Low latency cut-through switch architecture
x
Supports 128 to 2048 byte maximum payload size
x
One virtual channel
x
Fully compliant with PCI Express Base specification
Revision 1.0a
Flexible Architecture with
Numerous Configuration Options
x
Automatic per port link width negotiation to x8, x4, x2 or x1
x
Port arbitration schemes utilizing round robin or weighted
Diagram
Block Diagram
3-Port Switch Core
Frame Buffer
Route Table
Port
Arbitration
Scheduler
Transaction Layer
Data Link Layer
Transaction Layer
Data Link Layer
Transaction Layer
Data Link Layer
Multiplexer / Demultiplexer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Multiplexer / Demultiplexer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Multiplexer / Demultiplexer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
...
...
...
SerDes
SerDes
SerDes
SerDes
SerDes
SerDes
SerDes
SerDes
SerDes
24 PCI Express Lanes
x8 Upstream Port and Two x8 Downstream Ports
Figure 1 Internal Block Diagram
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
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2005 Integrated Device Technology, Inc.
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DSC 6803
IDT Product Brief
Power Management
x
Utilizes advanced low-power design techniques to achieve
low typical power consumption
x
Support PCI Express Power Management Interface
specification (PCI-PM 1.1)
x
Unused SerDes are disabled.
x
Supports Advanced Configuration and Power Interface
Specification, Revision 2.0 (ACPI) supporting active link
state
Testability and Debug Features
x
Support IEEE 1149.6 JTAG which extends the capability of
the IEEE 1149.1 standard to include AC-coupled and/or
differential nets
x
Built in Pseudo-Random Bit Stream (PRBS) generator
x
Numerous SerDes test modes
x
Ability to read and write any internal register via the SMBus
x
Ability to bypass link training and force any link into any
mode
x
Provides statistics and performance counters
8 General Purpose Input/Output pins
x
Each pin may be individually configured as an input or
output
x
Some pins have selectable alternate functions
Packaged in a 420-ball BGA
x
27x27 mm
x
1mm ball spacing
Product Description
Utilizing standard PCI Express interconnect, the PES24N3 provides
the most efficient high-performance I/O connectivity solution for applica-
tions requiring high throughput, low latency, and simple board layout
with a minimum number of board layers. It provides 12 GBps (96 Gbps)
of aggregated, full-duplex switching capacity through 24 integrated
serial lanes, using proven and robust IDT technology. Each lane
provides 2.5 Gbps of bandwidth in both directions and is fully compliant
with PCI Express Base specification 1.0a.
The PES24N3 is based on a flexible and efficient layered architec-
ture. The PCI Express layer consists of SerDes, Physical, Data Link and
Transaction layers in compliance with PCI Express Base specification
Revision 1.0a. The PES24N3 can operate either as a store and forward
or cut-through switch depending on the packet size and is designed to
switch memory and I/O transactions. It supports eight Traffic Classes
(TCs) and one Virtual Channel (VC) with sophisticated resource
management. This includes system selectable algorithms such as round
robin, weighted round-robin, and strict priority schemes guaranteeing
bandwidth allocation and/or latency for critical traffic classes in applica-
tions such as high throughput 10 Gigabit I/Os, SATA controllers, and
Fibre Channel HBAs.
Processor
North
Bridge
Memory
Memory
Memory
Memory
PES24N3
PES24N3
PES24N3
PCI Express
Slots
I/O
10GbE
I/O
10GbE
I/O
SATA
I/O
SATA
Figure 2 I/O Expansion Application
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
for Tech Support:
email: ssdhelp@idt.com
phone: 408-284-8208
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December 22, 2005
PCB Design
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