INTEGRATED CIRCUITS
SCN68681
Dual asynchronous receiver/transmitter
(DUART)
Product data
Supersedes data of 1998 Sep 04
2004 Mar 02
Philips
Semiconductors
Philips Semiconductors
Product data
Dual asynchronous receiver/transmitter (DUART)
SCN68681
DESCRIPTION
The Philips Semiconductors SCN68681 Dual Universal
Asynchronous Receiver/Transmitter (DUART) is a single-chip
MOS-LSI communications device that provides two independent
full-duplex asynchronous receiver/transmitter channels in a single
package. It is compatible with other S68000 family devices, and can
also interface easily with other microprocessors. The DUART can be
used in polled or interrupt driven systems.
The operating mode and data format of each channel can be
programmed independently. Additionally, each receiver and
transmitter can select its operating speed as one of eighteen fixed
baud rates, a 16X clock derived from a programmable counter/timer,
or an external 1X or 16X clock. The baud rate generator and
counter/timer can operate directly from a crystal or from external
clock inputs. The ability to independently program the operating
speed of the receiver and transmitter make the DUART particularly
attractive for dual-speed channel applications such as clustered
terminal systems.
Each receiver is quadruply buffered to minimize the potential of
receiver overrun or to reduce interrupt overhead in interrupt driven
systems. In addition, a flow control capability is provided to disable a
remote DUART transmitter when the buffer of the receiving device is
full.
Also provided on the SCN68681 are a multipurpose 6-bit input port
and a multipurpose 8-bit output port. These can be used as general
purpose I/O ports or can be assigned specific functions (such as
clock inputs or status/interrupt outputs) under program control.
•
16-bit programmable Counter/Timer
•
Parity, framing, and overrun error detection
•
False start bit detection
•
Line break detection and generation
•
Programmable channel mode
–
Normal (full-duplex)
–
Automatic echo
–
Local loopback
–
Remote loopback
•
Multi-function programmable 16-bit counter/timer
•
Multi-function 6-bit input port
–
Can serve as clock or control inputs
–
Change-of-state detection on four inputs
–
100 kΩ typical pull-up resistors
•
Multi-function 8-bit output port
–
Individual bit set/reset capability
–
Outputs can be programmed to be status/interrupt signals
•
Versatile interrupt system
–
Single interrupt output with eight maskable interrupting
conditions
–
Interrupt vector output on interrupt acknowledge
–
Output port can be configured to provide a total of up to six
separate wire-ORable interrupt outputs
FEATURES
•
S68000 bus compatible
•
Dual full-duplex asynchronous receiver/transmitter
•
Quadruple buffered receiver data registers
•
Programmable data format
–
5 to 8 data bits plus parity
–
Odd, even, no parity or force parity
–
1, 1.5 or 2 stop bits programmable in 1/16-bit increments
•
Maximum data transfer rates:
1X - 1 MB/sec, 16X - 125 kB/sec
•
Programmable baud rate for each receiver and transmitter
selectable from:
–
22 fixed rates: 50 to 115.2 k baud
–
Non-standard rates to 115.2 kb
–
Non-standard user-defined rate derived from programmable
counter/timer
–
External 1X or 16X clock
•
Automatic wake-up mode for multidrop applications
•
Start-end break interrupt/status
•
Detects break which originates in the middle of a character
•
On-chip crystal oscillator
•
Single +5 V power supply
•
Commercial and industrial temperature ranges available
•
DIP and PLCC packages
ORDERING INFORMATION
COMMERCIAL
DESCRIPTION
40-Pin Plastic Dual In-Line Package (DIP)
44-Pin Plastic Leaded Chip Carrier (PLCC)
V
CC
= +5 V + 5 %,
T
amb
= 0
°C
to +70
°C
SCN68681C1N40
SCN68681C1A44
INDUSTRIAL
V
CC
= +5 V + 10 %,
T
amb
= –40
°C
to +85
°C
SCN68681E1N40
SCN68681E1A44
DWG #
SOT129-1
SOT187-2
2004 Mar 02
2
Philips Semiconductors
Product data
Dual asynchronous receiver/transmitter (DUART)
SCN68681
PIN CONFIGURATIONS
A1
IP3
A2
IP1
A3
A4
IP0
R/WN
1
2
3
4
5
6
7
8
40 V
CC
39 IP4
6
38 IP5
37 IACKN
36 IP2
35 CSN
34 RESETN
33 X2
32 X1/CLK
31 RxDA
DIP
TxDB 11
OP1 12
OP3
13
30 TxDA
29 OP0
28 OP2
27 OP4
26 OP6
25 D0
24 D2
23 D4
22 D6
21 INTRN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
NC
A1
IP3
A2
IP1
A3
A4
IP0
R/WN
DTACKN
RxDB
NC
TxDB
OP1
OP3
17
18
PIN/FUNCTION
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
OP5
OP7
D1
D3
D5
D7
GND
NC
INTRN
D6
D4
D2
D0
OP6
OP4
31
32
33
34
35
36
37
38
39
40
41
42
43
44
OP2
OP0
TxDA
NC
RxDA
X1/CLK
X2
RESETN
CSN
IP2
IACKN
IP5
IP4
V
CC
28
29
PLCC
7
1
40
39
DTACKN 9
RxDB 10
OP5 14
OP7 15
D1 16
D3 17
D5 18
D7 19
GND 20
SD00107
Figure 1. Pin Configurations
ABSOLUTE MAXIMUM RATINGS
1
SYMBOL
T
amb
T
stg
PARAMETER
Operating ambient temperature range
2
Storage temperature range
All voltages with respect to ground
3
RATING
See Note 4
–65 to +150
–0.5 to +6.0
UNIT
°C
°C
V
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other condition above those indicated in the operation section of this specification is not
implied.
2. For operating at elevated temperatures, the device must be derated based on +150
°C
maximum junction temperature.
3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.
4. Parameters are valid over specified temperature range. See Ordering information table for applicable operating temperature range and V
CC
supply range.
2004 Mar 02
3
Philips Semiconductors
Product data
Dual asynchronous receiver/transmitter (DUART)
SCN68681
BLOCK DIAGRAM
8
D0–D7
BUS BUFFER
CHANNEL A
TRANSMIT
HOLDING REG
TRANSMIT
SHIFT REGISTER
TxDA
R/WN
DTACKN
CSN
A1–A4
RESETN
4
OPERATION CONTROL
ADDRESS
DECODE
R/W CONTROL
RECEIVE
HOLDING REG (3)
RxDA
RECEIVE
SHIFT REGISTER
MR1, 2
CRA
SRA
INTERRUPT CONTROL
INTRN
IMR
IACKN
ISR
IVR
INTERNAL DATABUS
CHANNEL B
(AS ABOVE)
TxDB
RxDB
INPUT PORT
CHANGE OF
STATE
DETECTORS (4)
IPCR
ACR
CONTROL
TIMING
BAUD RATE
GENERATOR
TIMING
6
IP0-IP5
CLOCK
SELECTORS
COUNTER/
TIMER
OUTPUT PORT
FUNCTION
SELECT LOGIC
8
X1/CLK
XTAL OSC
X2
CSRA
CSRB
ACR
U
CTLR
CTLR
OP0-OP7
OPCR
OPR
V
CC
GND
SD00108
Figure 2. Block Diagram
2004 Mar 02
4
Philips Semiconductors
Product data
Dual asynchronous receiver/transmitter (DUART)
SCN68681
PIN DESCRIPTION
SYMBOL
D0-D7
CSN
R/WN
A1-A4
RESETN
TYPE
I/O
I
I
I
I
NAME AND FUNCTION
Data Bus:
Bidirectional 3-State data bus used to transfer commands, data and status between the DUART and the
CPU. D0 is the least significant bit.
Chip Select:
Active-LOW input signal. When LOW, data transfers between the CPU and the DUART are enabled on
D0-D7 as controlled by the R/WN, RDN and A1-A4 inputs. When HIGH, places the D0-D7 lines in the 3-State condition.
Read/Write:
A HIGH input indicates a read cycle and a LOW input indicates a write cycle, when a cycle is initiated by
assertion of the CSN input.
Address Inputs:
Select the DUART internal registers and ports for read/write operations.
Reset:
A LOW level clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), initializes the IVR to hex 0F, puts
OP0-OP7 in the HIGH state, stops the counter/timer, and puts Channel A and B in the inactive state, with the TxDA
and TxDB outputs in the mark (HIGH) state. Clears Test modes, sets MR pointer to MR1.
Data Transfer Acknowledge:
Three-state active LOW output asserted in write, read, or interrupt cycles to indicate
proper transfer of data between the CPU and the DUART.
Interrupt Request:
Active-LOW, open-drain, output which signals the CPU that one or more of the eight maskable
interrupting conditions are true.
Interrupt Acknowledge:
Active-LOW input indicating an interrupt acknowledge cycle. In response, the DUART will
place the interrupt vector on the data bus and will assert DTACKN if it has an interrupt pending.
Crystal 1:
Crystal connection or an external clock input. A crystal of a clock the appropriate frequency (nominally
3.6864 MHz) must be supplied at all times. For crystal connections see Figure 9, Clock Timing.
Crystal 2:
Crystal connection. See Figure 9. If a crystal is not used it is best to keep this pin not connected although it
is permissible to ground it.
Channel A Receiver Serial Data Input:
The least significant bit is received first. “Mark” is HIGH, “space” is LOW.
Channel B Receiver Serial Data Input:
The least significant bit is received first. “Mark” is HIGH, “space” is LOW.
Channel A Transmitter Serial Data Output:
The least significant bit is transmitted first. This output is held in the
“mark” condition when the transmitter is disabled, idle or when operating in local loopback mode. “Mark” is HIGH,
“space” is LOW.
Channel B Transmitter Serial Data Output:
The least significant bit is transmitted first. This output is held in the
‘mark’ condition when the transmitter is disabled, idle, or when operating in local loopback mode. ‘Mark’ is HIGH,
‘space’ is LOW.
Output 0:
General purpose output or Channel A request to send (RTSAN, active-LOW). Can be deactivated
automatically on receive or transmit.
Output 1:
General purpose output or Channel B request to send (RTSBN, active-LOW). Can be deactivated
automatically on receive or transmit.
Output 2:
General purpose output, or Channel A transmitter 1X or 16X clock output, or Channel A receiver 1X clock
output.
Output 3:
General purpose output or open-drain, active-LOW counter/timer output or Channel B transmitter 1X clock
output, or Channel B receiver 1X clock output.
Output 4:
General purpose output or Channel A open-drain, active-LOW, RxRDYA/FFULLA output.
Output 5:
General purpose output or Channel B open-drain, active-LOW, RxRDYB/FFULLB output.
Output 6:
General purpose output or Channel A open-drain, active-LOW, TxRDYA output.
Output 7:
General purpose output, or Channel B open-drain, active-LOW, TxRDYB output.
Input 0:
General purpose input or Channel A clear to send active-LOW input (CTSAN). Pin has an internal V
CC
pull-up device supplying 1 to 4
µA
of current.
Input 1:
General purpose input or Channel B clear to send active-LOW input (CTSBN). Pin has an internal V
CC
pull-up device supplying 1 to 4
µA
of current.
Input 2:
General purpose input, or Channel B receiver external clock input (RxCB), or counter/timer external clock
input. When the external clock is used by the receiver, the received data is sampled on the rising edge of the clock.
Pin has an internal V
CC
pull-up device supplying 1 to 4
µA
of current.
Input 3:
General purpose input or Channel A transmitter external clock input (TxCA). When the external clock is used
by the transmitter, the transmitted data is clocked on the falling edge of the clock. Pin has an internal V
CC
pull-up
device supplying 1 to 4
µA
of current.
Input 4:
General purpose input or Channel A receiver external clock input (RxCA). When the external clock is used
by the receiver, the received data is sampled on the rising edge of the clock. Pin has an internal V
CC
pull-up device
supplying 1 to 4
µA
of current.
Input 5:
General purpose input or Channel B transmitter external clock input (TxCB). When the external clock is used
by the transmitter, the transmitted data is clocked on the falling edge of the clock. Pin has an internal V
CC
pull-up
device supplying 1 to 4
µA
of current.
Power Supply:
+5 V supply input.
Ground.
DTACKN
INTRN
IACKN
X1/CLK
X2
RxDA
RxDB
TxDA
O
O
I
I
I
I
I
O
TxDB
O
OP0
OP1
OP2
OP3
OP4
OP5
OP6
OP7
IP0
IP1
IP2
O
O
O
O
O
O
O
O
I
I
I
IP3
I
IP4
I
IP5
I
V
CC
GND
I
I
2004 Mar 02
5
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