Intel
®
Xeon
®
Processor 3400 Series
Datasheet – Volume 2
January 2010
Document Number: 322372-002
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED,
BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS
PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER,
AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING
LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY
PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving,
life sustaining, critical control or safety systems, or in nuclear facility applications.
Legal Lines and Disclaimers
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel
reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future
changes to them.
The Intel
®
Xeon
®
processor 3400 series may contain design defects or errors known as errata which may cause the product to
deviate from published specifications. Current characterized errata are available on request.
Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor
family, not across different processor families. See http://www.intel.com/products/processor_number for details. Over time
processor numbers will increment based on changes in clock, speed, cache, FSB, or other features, and increments are not
intended to represent proportional or quantitative increases in any particular feature. Current roadmap processor number
progression is not necessarily representative of future roadmaps. See www.intel.com/products/processor_number for details.
No computer system can provide absolute security under all conditions. Intel® Trusted Execution Technology (Intel® TXT) requires
a computer system with Intel® Virtualization Technology, an Intel TXT-enabled processor, chipset, BIOS, Authenticated Code
Modules and an Intel TXT-compatible measured launched environment (MLE). The MLE could consist of a virtual machine monitor,
an OS or an application. In addition, Intel TXT requires the system to contain a TPM v1.2, as defined by the Trusted Computing
Group and specific software for some uses. For more information, see
http://www.intel.com/technology/security/.
Intel® Virtualization Technology requires a computer system with an enabled Intel® processor, BIOS, virtual machine monitor
(VMM) and, for some uses, certain platform software enabled for it. Functionality, performance or other benefits will vary
depending on hardware and software configurations and may require a BIOS update. Software applications may not be compatible
with all operating systems. Please check with your application vendor.
Intel
®
Active Management Technology requires the computer system to have an Intel(R) AMT-enabled chipset, network hardware
and software, as well as connection with a power source and a corporate network connection. Setup requires configuration by the
purchaser and may require scripting with the management console or further integration into existing security frameworks to
enable certain functionality. It may also require modifications of implementation of new business processes. With regard to
notebooks, Intel AMT may not be available or certain capabilities may be limited over a host OS-based VPN or when connecting
wirelessly, on battery power, sleeping, hibernating or powered off. For more information, see www.intel.com/technology/platform-
technology/intel-amt/
Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting
operating system. Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Intel literature may be obtained
by calling 1-800-548-4725 or by visiting Intel's website at
http://www.intel.com.
Intel, Intel Xeon, Intel Scalable Memory Interconnect (Intel SMI), Intel Virtualization Technology for Directed I/O, Intel Trusted
Execution Technology (Intel TXT), Intel Management Engine (Intel ME), Intel Interconnect BIST (Intel IBIST), and the Intel logo
are trademarks of Intel Corporation in the U. S. and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2009–2010, Intel Corporation. All Rights Reserved.
Δ
2
Datasheet, Volume 2
Contents
1
2
Introduction
............................................................................................................ 17
1.1
Register Terminology ......................................................................................... 17
Configuration Process and Registers
....................................................................... 19
2.1
Platform Configuration Structure ......................................................................... 19
2.1.1 Processor Integrated I/O (IIO) Devices (PCI Bus 0) .................................... 19
2.1.2 Processor Uncore Devices (PCI Bus — FFh) ................................................ 20
2.2
Configuration Mechanisms .................................................................................. 21
2.2.1 Standard PCI Express* Configuration Mechanism........................................ 21
2.2.2 PCI Express* Configuration Mechanism ..................................................... 21
2.3
Routing Configuration Accesses ........................................................................... 23
2.3.1 Internal Device Configuration Accesses ..................................................... 24
2.3.2 Bridge-Related Configuration Accesses ...................................................... 24
2.3.2.1 PCI Express* Configuration Accesses ........................................... 24
2.3.2.2 DMI Configuration Accesses ....................................................... 25
2.4
Processor Register Introduction ........................................................................... 25
2.5
I/O Mapped Registers ........................................................................................ 26
Processor Integrated I/O (IIO) Configuration Registers
......................................... 27
3.1
Processor IIO Devices (PCI Bus 0) ....................................................................... 27
3.2
Device Mapping................................................................................................. 28
3.2.1 Unimplemented Devices/Functions and Registers........................................ 28
3.3
PCI Express*/DMI Configuration Registers ............................................................ 28
3.3.1 Other Register Notes .............................................................................. 28
3.3.2 Configuration Register Map ...................................................................... 29
3.3.3 Standard PCI Configuration Space (0h to 3Fh) —
Type 0/1 Common Configuration Space ..................................................... 35
3.3.3.1 VID—Vendor Identification Register............................................. 35
3.3.3.2 DID—Device Identification Register ............................................. 35
3.3.3.3 PCICMD—PCI Command Register ................................................ 36
3.3.3.4 PCISTS—PCI Status Register ...................................................... 38
3.3.3.5 RID—Revision Identification Register ........................................... 40
3.3.3.6 CCR—Class Code Register .......................................................... 40
3.3.3.7 CLSR—Cacheline Size Register.................................................... 41
3.3.3.8 PLAT—Primary Latency Timer ..................................................... 41
3.3.3.9 HDR—Header Type Register ....................................................... 41
3.3.3.10 SVID—Subsystem Vendor ID ...................................................... 42
3.3.3.11 SID—Subsystem Identity ........................................................... 42
3.3.3.12 CAPPTR—Capability Pointer ........................................................ 42
3.3.3.13 INTLIN—Interrupt Line Register .................................................. 42
3.3.3.14 INTPIN—Interrupt Pin Register ................................................... 43
3.3.3.15 PBUS—Primary Bus Number Register........................................... 43
3.3.3.16 SECBUS—Secondary Bus Number ............................................... 43
3.3.3.17 SUBBUS—Subordinate Bus Number Register................................. 44
3.3.3.18 IOBAS—I/O Base Register.......................................................... 44
3.3.3.19 IOLIM—I/O Limit Register .......................................................... 45
3.3.3.20 SECSTS—Secondary Status Register ........................................... 46
3.3.3.21 MBAS—Memory Base ................................................................ 47
3.3.3.22 MLIM—Memory Limit ................................................................. 47
3.3.3.23 PMBASE—Prefetchable Memory Base Register............................... 48
3.3.3.24 PMLIMIT—Prefetchable Memory Limit .......................................... 48
3.3.3.25 PMBASEU—Prefetchable Memory Base (Upper 32 bits) ................... 49
3.3.3.26 PMLIMITU—Prefetchable Memory Limit (Upper 32 bits) .................. 49
3.3.3.27 BCTRL—Bridge Control Register .................................................. 50
3.3.4 Device-Specific PCI Configuration Space — 40h to FFh ................................ 51
3.3.4.1 SCAPID—Subsystem Capability Identity ....................................... 51
3
Datasheet, Volume 2
3
3.4
SNXTPTR—Subsystem ID Next Pointer .........................................51
SVID—Subsystem Vendor ID ......................................................52
SID—Subsystem Identity ...........................................................52
DMIRCBAR—DMI Root Complex Register Block Base Address
Register ...................................................................................52
3.3.4.6 MSICAPID—MSI Capability ID .....................................................53
3.3.4.7 MSINXTPTR—MSI Next Pointer ....................................................53
3.3.4.8 MSICTRL—MSI Control Register...................................................53
3.3.4.9 MSIAR—MSI Address Register .....................................................54
3.3.4.10 MSIDR—MSI Data Register .........................................................55
3.3.4.11 MSIMSK—MSI Mask Bit Register..................................................55
3.3.4.12 MSIPENDING—MSI Pending Bit Register .......................................56
3.3.4.13 PEGCAPID—PCI Express* Capability Identity Register ....................56
3.3.4.14 PEGNXTPTR—PCI Express* Next Pointer Register...........................56
3.3.4.15 PEGCAP—PCI Express* Capabilities Register .................................57
3.3.4.16 DEVCAP—PCI Express* Device Capabilities Register .......................58
3.3.4.17 DEVCTRL—PCI Express* Device Control Register ...........................59
3.3.4.18 DEVSTS—PCI Express* Device Status Register ..............................61
3.3.4.19 LNKCAP—PCI Express* Link Capabilities Register...........................62
3.3.4.20 LNKCON—PCI Express* Link Control Register (Device 0) ................64
3.3.4.21 LNKCON—PCI Express* Link Control Register ................................65
3.3.4.22 LNKSTS—PCI Express* Link Status Register..................................66
3.3.4.23 SLTCAP—PCI Express* Slot Capabilities Register ...........................68
3.3.4.24 SLTCON—PCI Express* Slot Control Register.................................69
3.3.4.25 ROOTCON—PCI Express* Root Control Register.............................70
3.3.4.26 ROOTCAP—PCI Express* Root Capabilities Register........................71
3.3.4.27 ROOTSTS—PCI Express* Root Status Register...............................72
3.3.4.28 DEVCAP2—PCI Express* Device Capabilities Register 2 ..................73
3.3.4.29 DEVCTRL2—PCI Express* Device Control Register 2.......................74
3.3.4.30 LNKCON2—PCI Express* Link Control Register 2 ...........................75
3.3.4.31 LNKSTS2—PCI Express* Link Control Register 2 ............................76
3.3.4.32 PMCAP—Power Management Capabilities Register ..........................76
3.3.4.33 PMCSR—Power Management Control and Status
Register (Device 0 DMI) .............................................................77
3.3.4.34 PMCSR—Power Management Control and Status Register................78
3.3.5 PCIe/DMI Extended Configuration Space ....................................................79
3.3.5.1 APICBASE—APIC Base Register ...................................................79
3.3.5.2 APICLIMIT—APIC Limit Register ..................................................79
3.3.5.3 PERFCTRLSTS—Performance Control and Status Register................79
3.3.5.4 MISCCTRLSTS—Miscellaneous Control and Status Register..............81
3.3.5.5 CTOCTRL—Completion Time-out Control Register ..........................83
3.3.6 DMI Root Complex Register Block .............................................................84
3.3.6.1 DMIVCH—DMI Virtual Channel Capability Header ...........................85
3.3.6.2 DMIVCCAP1—DMI Port VC Capability Register 1 ............................85
3.3.6.3 DMIVCCAP2—DMI Port VC Capability Register 2 ............................86
3.3.6.4 DMIVCCTL—DMI Port VC Control .................................................86
3.3.6.5 DMIVC0RCAP—DMI VC0 Resource Capability .................................87
3.3.6.6 DMIVC0RCTL—DMI VC0 Resource Control.....................................87
3.3.6.7 DMIVC0RSTS—DMI VC0 Resource Status......................................88
3.3.6.8 DMIVC1RCAP—DMI VC1 Resource Capability .................................88
3.3.6.9 DMIVC1RCTL—DMI VC1 Resource Control.....................................89
3.3.6.10 DMIVC1RSTS—DMI VC1 Resource Status......................................90
3.3.6.11 DMILCAP—DMI Link Capabilities ..................................................90
3.3.6.12 DMILCTRL—DMI Link Control ......................................................91
3.3.6.13 DMILSTS—DMI Link Status .........................................................91
Integrated I/O Core Registers (Device 8, Function 0-3)...........................................92
3.4.1 Configuration Register Map (Device 8, Function 0-3) ...................................92
3.4.2 Standard PCI Configuration Registers ........................................................98
3.4.2.1 VID—Vendor Identification Register .............................................98
3.4.2.2 DID—Device Identification Register..............................................98
3.4.2.3 PCICMD—PCI Command Register ................................................98
3.3.4.2
3.3.4.3
3.3.4.4
3.3.4.5
4
Datasheet, Volume 2
3.4.3
3.4.4
3.4.5
3.4.2.4 PCISTS—PCI Status Register .................................................... 100
3.4.2.5 RID—Revision Identification Register ......................................... 102
3.4.2.6 CCR—Class Code Register ........................................................ 102
3.4.2.7 CLSR—Cacheline Size Register.................................................. 102
3.4.2.8 HDR—Header Type Register ..................................................... 103
3.4.2.9 SVID—Subsystem Vendor ID .................................................... 103
3.4.2.10 SID—Subsystem Device ID ...................................................... 103
3.4.2.11 CAPPTR—Capability Pointer ...................................................... 103
3.4.2.12 INTLIN—Interrupt Line Register ................................................ 104
3.4.2.13 INTPIN—Interrupt Pin Register ................................................. 104
Common Extended Configuration Space Registers..................................... 104
3.4.3.1 CAPID—PCI Express
®
Capability List Register ............................. 104
3.4.3.2 NXTPTR—PCI Express
®
Next Capability List Register.................... 105
3.4.3.3 EXPCAP—PCI Express
®
Capabilities Register............................... 105
3.4.3.4 DEVCAP—PCI Express
®
Device Capabilities Register .................... 106
3.4.3.5 DEVCTRL—PCI Express
®
Device Control Register ........................ 107
3.4.3.6 DEVSTS—PCI Express
®
Device Status Register ........................... 109
Intel
®
VT-d, Address Mapping, System Management Registers (Device 8,
Function 0).......................................................................................... 110
3.4.4.1 IIOMISCCTRL—Integrated I/O Misc Control Register .................... 110
3.4.4.2 IIOMISCSS—Integrated I/O MISC Status ................................... 111
3.4.4.3 TSEGCTRL—TSEG Control Register ............................................ 111
3.4.4.4 TOLM—Top of Low Memory ...................................................... 112
3.4.4.5 TOHM—Top of High Memory ..................................................... 112
3.4.4.6 NCMEM.BASE—NCMEM Base .................................................... 112
3.4.4.7 NCMEM.LIMIT—NCMEM Limit .................................................... 113
3.4.4.8 DEVHIDE1—Device Hide 1 Register ........................................... 113
3.4.4.9 DEVHIDE2—Device Hide 2 Register ........................................... 116
3.4.4.10 IIOBUSNO—IIO Internal Bus Number ........................................ 117
3.4.4.11 LMMIOL.BASE—Local MMIOL Base............................................. 117
3.4.4.12 LMMIOL.LIMIT—Local MMIOL Limit ............................................ 118
3.4.4.13 LMMIOH.BASE—Local MMIOH Base............................................ 118
3.4.4.14 LMMIOH.LIMIT—Local MMIOH Limit ........................................... 118
3.4.4.15 LMMIOH.BASEU—Local MMIOH Base Upper ................................ 119
3.4.4.16 LMMIOH.LIMITU—Local MMIOH Limit Upper................................ 119
3.4.4.17 LCFGBUS.BASE—Local Configuration Bus Number Base Register ... 119
3.4.4.18 LCFGBUS.LIMIT—Local Configuration Bus Number Limit Register... 120
3.4.4.19 GMMIOL.BASE—Global MMIOL Base .......................................... 120
3.4.4.20 GMMIOL.LIMIT—Global MMIOL Limit.......................................... 120
3.4.4.21 GMMIOH.BASE—Global MMIOH Base ......................................... 121
3.4.4.22 GMMIOH.LIMIT—Global MMIOH Limit......................................... 121
3.4.4.23 GMMIOH.BASEU—Global MMIOH Base Upper .............................. 122
3.4.4.24 GMMIOH.LIMITU—Global MMIOH Limit Upper ............................. 122
3.4.4.25 GCFGBUS.BASE—Global Configuration Bus Number Base Register . 122
3.4.4.26 GCFGBUS.LIMIT—Global Configuration Bus Number Limit Register. 123
3.4.4.27 MESEGBASE—Intel
®
Management Engine (Intel
®
ME)
Memory Region Base ............................................................... 123
3.4.4.28 MESEGMASK—Intel
®
ME Memory Region Mask ........................... 123
3.4.4.29 VTBAR—Base Address Register for Intel
®
VT-d Chipset Registers .. 124
3.4.4.30 VTGENCTRL—Intel
®
VT-d General Control Register...................... 125
3.4.4.31 VTISOCHCTRL—Intel VT-d Isoch Related Control Register ............ 126
3.4.4.32 VTGENCTRL2—Intel VT-d General Control 2 Register ................... 126
3.4.4.33 VTSTS—Intel
®
VT-d Status Register .......................................... 127
Semaphore and ScratchPad Registers (Dev:8, F:1) ................................... 127
3.4.5.1 SR[0:3]—Scratch Pad Register 0-3 (Sticky) ................................ 127
3.4.5.2 SR[4:7]—Scratch Pad Register 4-7 (Sticky) ................................ 127
3.4.5.3 SR[8:11]—Scratch Pad Register 8-11 (Non-Sticky)...................... 127
3.4.5.4 SR[12:15]—Scratch Pad Register 12-15 (Non-Sticky) .................. 128
3.4.5.5 SR[16:17]—Scratch Pad Register 16-17 (Non-Sticky) .................. 128
3.4.5.6 SR[18:23]—Scratch Pad Register 18-23 (Non-Sticky) .................. 128
3.4.5.7 CWR[0:3]—Conditional Write Registers 0-3 ................................ 128
Datasheet, Volume 2
5
京公网安备 11010802033920号
EEWORLD
