PRELIMINARY DATA SHEET
512M bits XDR
DRAM
EDX5116ABSE (32M words
×
16 bits)
Overview
The EDX5116ABSE is a 512M bits XDR
™
DRAM organized
as 32M words
×
16 bits. It is a general-purpose high-perfor-
mance memory device suitable for use in a broad range of
applications.
The use of Differential Rambus Signaling Level (DRSL) tech-
nology permits 4000/3200/2400 Mb/s transfer rates while
using conventional system and board design technologies.
XDR DRAM devices are capable of sustained data transfers of
8000/6400/4800 MB/s.
XDR DRAM device architecture allows the highest sustained
bandwidth for multiple, interleaved randomly addressed mem-
ory transactions. The highly-efficient protocol yields over 95%
utilization while allowing fine access granularity. The device’s
eight banks support up to four interleaved transactions.
It is packaged in 104-ball FBGA (
µ
BGA
) compatible with
Rambus XDR DRAM pin configuration.
•
Low power
• 1.8V Vdd
• Programmable small-swing I/O signaling (DRSL)
• Low power PLL/DLL design
• Powerdown self-refresh support
• Per pin I/O powerdown for narrow-width operation
Pin Configuration
L
1
DQN3
DQN9
K
J
VDD
VDD
H
GND
G
VDD
F
Row
E
GND
D
VDD
C
SDI
GND
B
A
2
DQ3
1
2
3
4
5
6
7
DQN8 DQN2
DQ8
DQ2
DQ9
3
4
5
6
7
8
DQN15
DQ15
P
DQ5
DQN5
DQN5 VDD RQ10
CFM
RSRV
RSRV
VDD
DQN7 RQ0 DQN4
DQ7
RQ4
DQN14
VTERM GND
GND DQ4
RQ3
DQN3 VTERM VDD
DQ3
DQ14
VDD
GND
N
GND
VDD
DQ5 GND RQ11 CFMN
DQ1
DQN1
VDD VTERM
GND
GND
VDD
VDD
VREF
GND
VDD
VTERM
RQ10GND
RQ8
RQ6
RQ4
RQ2
RQ0 GND
VDD
GND
VDD
RQ7
RQ6
GND
GND
M
VDD
L
K
J
GND
VDD
RQ11
VDD
RQ9
RQ7
CFMN
RQ5
GND GND
VDD
GND
CFM
GND
Column
9
10
H
G
F
E
D
C
B
A
Features
•
Highest pin bandwidth available
4000/3200/2400 Mb/s Octal Data Rate (ODR) Signaling
• Bi-directional differential RSL (DRSL)
- Flexible read/write bandwidth allocation
- Minimum pin count
• On-chip termination
-Adaptive impedance matching
-Reduced system cost and routing complexity
Highest sustained bandwidth per DRAM device
• 8000/6400/4800 MB/s sustained data rate
• Eight banks: bank-interleaved transactions at full
bandwidth
• Dynamic request scheduling
• Early-read-after-write support for maximum efficiency
• Zero overhead refresh
Dynamic width control
•EDX5116ABSE supports
×
16,
×
8 and
×
4 mode
Low latency
• 2.0/2.5/3.33 ns request packets
• Point-to-point data interconnect for fastest possible
flight time
• Support for low-latency, fast-cycle cores
11
12
13
14
15
16
GND
VDD
GND
RQ3
VDD
RQ1
VDD
VTERM GND
GND
GND
GND
VDD
GND
RST
GND GND
SD0
CMD
DQN13 VDD
RQ9
DQ0
DQN0
DQ13 CMD
RQ8
DQN7
DQ7
VREF
RQ5
SCK
RQ1
SD1
VDD DQN12 DQN6
DQ6
DQN2
DG2
RQ2
GND DQ12
VTERM
GND
VDD
DQN11 DQN1 SCK
DQ11
DQ4
DQN4
GND
DQ1
VDD
VDD
GND
GND
RST DQN0 DQN10
DQ10
DQN6
DQ6
VDD
SDO
DQ0
A16
A8
Top view of package
•
•
•
Doc. No. E0643E30 (Ver. 3.0)
Date Published August 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc.
2005
EDX5116ABSE
Ordering Information
Part number
EDX5116ABSE-4C-E
EDX5116ABSE-3C-E
EDX5116ABSE-3B-E
EDX5116ABSE-3A-E
EDX5116ABSE-2A-E
Organization
Bandwidth (1/tBIT)
Latency (tRAC)
28
35
35
27
36
Bin
C
C
B
A
A
Package
104-ball FBGA
(µBGA)
4M
×
16
×
8 banks 4.0G
3.2G
3.2G
3.2G
2.4G
Part Number
E D X 51 16 A B SE - 4C - E
Elpida Memory
Type
D: Monolithic Device
Product Family
X: XDR DRAM
Density
25: 256M (x 16bit)
Organization
16: x16bit
Power Supply, Interface
A: 1.8V, DRSL
Environment Code
E: Lead Free
Speed
4C: 4.0G (tRAC = 28, C Bin)
3C: 3.2G (tRAC = 35, C Bin)
3B: 3.2G (tRAC = 35, B Bin)
3A: 3.2G (tRAC = 27, A Bin)
2A: 2.4G (tRAC = 36, A Bin)
Package
SE: FBGA
(µBGA with back cover)
Die Rev.
Preliminary Data Sheet E0643E30 (Ver. 3.0)
2
EDX5116ABSE
General Description
The timing diagrams in Figure 1 illustrate XDR DRAM device
write and read transactions. There are three sets of pins used
for normal memory access transactions: CFM/CFMN clock
pins, RQ11..0 request pins, and DQ15..0/DQN15..0 data pins.
The “N” appended to a signal name denotes the complemen-
tary signal of a differential pair.
A
transaction
is a collection of packets needed to complete a
memory access. A
packet
is a set of bit windows on the signals
of a bus. There are two buses that carry packets: the RQ bus
and DQ bus. Each packet on the RQ bus uses a set of 2 bit-
windows on each signal, while the DQ bus uses a set of 16 bit-
windows on each signal.
In the write transaction shown in Figure 1, a request packet (on
the RQ bus) at clock edge T
0
contains an activate (ACT) com-
Figure 1
XDR DRAM Device Write and Read Transactions
T
0
CFM
CFMN
RQ11..0
ACT WR
a0
a1
WR
a2
mand. This causes row Ra of bank Ba in the memory compo-
nent to be loaded into the sense amp array for the bank. A
second request packet at clock edge T
1
contains a write (WR)
command. This causes the data packet D(a1) at edge T
4
to be
written to column Ca1 of the sense amp array for bank Ba. A
third request packet at clock edge T
3
contains another write
(WR) command. This causes the data packet D(a2) at edge T
6
to be also written to column Ca2. A final request packet at
clock edge T
14
contains a precharge (PRE) command.
The spacings between the request packets are constrained by
the following timing parameters in the diagram: t
RCD -W
, t
CC
,
and t
WRP
. In addition, the spacing between the request packets
and data packets are constrained by the t
CWD
parameter. The
spacing of the CFM/CFMN clock edges is constrained by
t
CYCLE
.
T
1
T
2
T
3
T
4
T
5
T
6
T
7
T
8
T
9
T
10
T
11
T
12
T
13
T
14
T
15
T
16
T
17
T
18
T
19
T
20
T
21
T
22
T
23
t
DQ15..0
RCD-W
DQN15..0
t
CC
t
CWD
D(a1)
D(a2)
t
WRP
PRE
a3
t
CYCLE
Transaction a:
WR
a0 = {Ba,Ra}
a1 = {Ba,Ca1}
a2 = {Ba,Ca2}
a3 = {Ba}
Write Transaction
T
0
CFM
CFMN
RQ11..0
DQ15..0
DQN15..0
ACT
a0
RD
a1
RD
a2
PRE
a3
T
1
T
2
T
3
T
4
T
5
T
6
T
7
T
8
T
9
T
10
T
11
T
12
T
13
T
14
T
15
T
16
T
17
T
18
T
19
T
20
T
21
T
22
T
23
t
CYCLE
Q(a1)
Q(a2)
t
RCD-R
t
CC
t
RDP
t
CAC
Transaction a:
RD
a0 = {Ba,Ra}
a1 = {Ba,Ca1}
a2 = {Ba,Ca2}
a3 = {Ba}
Read Transaction
The read transaction shows a request packet at clock edge T
0
containing an ACT command. This causes row Ra of bank Ba
of the memory component to load into the sense amp array for
the bank. A second request packet at clock edge T
5
contains a
read (RD) command. This causes the data packet Q(a1) at edge
T
11
to be read from column Ca1 of the sense amp array for
bank Ba. A third request packet at clock edge T
7
contains
another RD command. This causes the data packet Q(a2) at
edge T
13
to also be read from column Ca2. A final request
packet at clock edge T
10
contains a PRE command. The spac-
ings between the request packets are constrained by the follow-
ing timing parameters in the diagram: t
RCD -R
, t
CC
, and t
RDP
.
In addition, the spacing between the request and data packets
are constrained by the t
CAC
parameter.
Preliminary Data Sheet E0643E30 (Ver. 3.0)
3
EDX5116ABSE
Table of Contents
Overview ....................................................................... 1
Features ........................................................................ 1
Pin Configuration ......................................................... 1
Ordering Information ................................................... 2
Part Number .................................................................2
General Description ......................................................3
Table of Contents .........................................................4
Pin Description .............................................................7
Block Diagram ..............................................................8
Request Packets ......................................................... 10
Request Packet Formats ................................................. 10
Request Field Encoding .................................................. 12
Request Packet Interactions ........................................... 14
Request Interaction Cases .............................................. 15
Dynamic Request Scheduling ........................................ 20
Memory Operations .................................................... 22
Write Transactions .......................................................... 22
Read Transactions ........................................................... 24
Interleaved Transactions ................................................. 26
Read/Write Interaction .................................................. 28
Propagation Delay ........................................................... 28
Register Operations .................................................... 32
Serial Transactions ........................................................... 32
Serial Write Transaction ................................................. 32
Serial Read Transaction .................................................. 32
Register Summary ............................................................ 34
Maintenance Operations ............................................ 40
Refresh Transactions ....................................................... 40
Interleaved Refresh Transactions .................................. 40
Calibration Transactions ................................................. 42
Power State Management ............................................... 44
Initialization ...................................................................... 46
XDR DRAM Initialization Overview .......................... 47
XDR DRAM Pattern Load with WDSL Reg ............. 48
Special Feature Description ....................................... 50
Dynamic Width Control ................................................. 50
Write Masking .................................................................. 52
Multiple Bank Sets and the ERAW Feature ................ 54
Simultaneous Activation ................................................. 56
Simultaneous Precharge ................................................. 57
Operating Conditions ................................................ 58
Electrical Conditions ....................................................... 58
Timing Conditions .......................................................... 59
Operating Characteristics .......................................... 60
Electrical Characteristics ................................................ 60
Supply Current Profile .................................................... 61
Timing Characteristics .................................................... 62
Timing Parameters .......................................................... 62
Receive/Transmit Timing ......................................... 64
Clocking ............................................................................ 64
RSL RQ Receive Timing ................................................ 65
DRSL DQ Receive Timing ............................................ 66
DRSL DQ Transmit Timing ......................................... 68
Serial Interface Receive Timing ..................................... 70
Serial Interface Transmit Timing .................................. 71
Package Description .................................................. 72
Package Parasitic Summary ............................................ 72
Package Drawing ............................................................ 74
Package Pin Numbering ................................................. 75
Recommended Soldering Conditions ....................... 76
Preliminary Data Sheet E0643E30 (Ver. 3.0)
4
EDX5116ABSE
List of Tables
Pin Description .............................................................7
Request Field Description .......................................... 10
OP Field Encoding Summary .................................... 12
ROP Field Encoding Summary .................................. 12
POP Field Encoding Summary .................................. 13
XOP Field Encoding Summary .................................. 13
Packet Interaction Summary ...................................... 14
SCMD Field Encoding Summary ............................... 32
Initialization Timing Parameters ............................... 47
XDR DRAM WDSL-to-Core/DQ/SC Map (First Genera-
tion x16/x8/x4 XDR DRAM , BL=16) ...................... 48
Core Data Word-to-WDSL Format ............................ 49
Electrical Conditions .................................................. 58
Timing Conditions ..................................................... 59
Electrical Characteristics ........................................... 60
Supply Current Profile .................................................61
Timing Characteristics ............................................... 62
Timing Parameters .................................................... 62
Package Parasitic Summary ....................................... 72
Preliminary Data Sheet E0643E30 (Ver. 3.0)
5
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