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601G-01ILF

Description
TSSOP-16, Tube
CategoryMicrocontrollers and processors    The clock generator   
File Size382KB,10 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance  
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601G-01ILF Overview

TSSOP-16, Tube

601G-01ILF Parametric

Parameter NameAttribute value
Brand NameIntegrated Device Technology
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeTSSOP
package instructionTSSOP, TSSOP16,.25
Contacts16
Manufacturer packaging codePGG16
Reach Compliance Codecompliant
ECCN codeEAR99
Samacsys DescriptionTSSOP 4.4 MM 0.65MM PITCH
JESD-30 codeR-PDSO-G16
JESD-609 codee3
length5 mm
Humidity sensitivity level1
Number of terminals16
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Maximum output clock frequency156 MHz
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Encapsulate equivalent codeTSSOP16,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply3.3/5 V
Master clock/crystal nominal frequency27 MHz
Certification statusNot Qualified
Maximum seat height1.2 mm
Maximum slew rate30 mA
Maximum supply voltage5.5 V
Minimum supply voltage3 V
Nominal supply voltage3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceMatte Tin (Sn) - annealed
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width4.4 mm
uPs/uCs/peripheral integrated circuit typeCLOCK GENERATOR, OTHER
Base Number Matches1
DATASHEET
LOW PHASE NOISE CLOCK MULTIPLIER
Description
The ICS601-01 is a low-cost, low phase noise,
high-performance clock synthesizer for applications
which require low phase noise and low jitter. It is IDT’s
lowest phase noise multiplier, and also the lowest
CMOS part in the industry. Using IDT’s patented
analog and digital Phase-Locked Loop (PLL)
techniques, the chip accepts a 10 - 27 MHz crystal or
clock input, and produces output clocks up to 156 MHz
at 3.3 V.
This product is intended for clock generation. It has low
output jitter (variation in the output period), but input to
output skew and jitter are not defined nor guaranteed.
For applications which require definted input to output
timing, use the ICS670-01.
ICS601-01
Features
Packaged in 16-pin SOIC or TSSOP
Pb (lead) free package
Uses fundamental 10 - 27 MHz crystal or clock
Patented PLL with the lowest phase noise
Output clocks up to 156 MHz at 3.3 V
Low phase noise: -132 dBc/Hz at 10 kHz
Low jitter - 18 ps one sigma typ.
Full swing CMOS outputs with 25 mA drive capability
at TTL levels
Advanced, low power, sub-micron CMOS process
Industrial temperature range available
Operating voltage of 3.3V or 5V
Block Diagram
VDD
3
Reference
Divider
Phase
Comparator
Charge
Pump
Loop
Filter
VCO
CLK
X1/ICLK
Crystal or
clock input
Crystal
Oscillator
X2
ROM Based
Multipliers
REFOUT
VCO
Divide
4
S3:0
3
GND
OE
REFEN
IDT™ / ICS™
LOW PHASE NOISE CLOCK MULTIPLIER
1
ICS601-01
REV N 051310

601G-01ILF Related Products

601G-01ILF ESXE800ETD391MK40C 601M-01LFT 601M-01ILFT 601G-01LFT
Description TSSOP-16, Tube Aluminum Electrolytic Capacitor, Polarized, Aluminum, 80V, 20% +Tol, 20% -Tol, 390uF, SOIC-16, Reel SOIC-16, Reel TSSOP-16, Reel
package instruction TSSOP, TSSOP16,.25 , SOP, SOP16,.25 SOIC-16 TSSOP, TSSOP16,.25
Reach Compliance Code compliant unknown compliant compliant compliant
ECCN code EAR99 EAR99 EAR99 EAR99 EAR99
length 5 mm 40 mm 9.9 mm 9.9 mm 5 mm
Number of terminals 16 2 16 16 16
Maximum operating temperature 85 °C 105 °C 70 °C 85 °C 70 °C
Minimum operating temperature -40 °C -55 °C - -40 °C -
Package form SMALL OUTLINE, THIN PROFILE, SHRINK PITCH Radial SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Terminal pitch 0.65 mm 5 mm 1.27 mm 1.27 mm 0.65 mm
Brand Name Integrated Device Technology - Integrated Device Technology Integrated Device Technology Integrated Device Technology
Is it lead-free? Lead free - Lead free Lead free Lead free
Is it Rohs certified? conform to - conform to conform to conform to
Maker IDT (Integrated Device Technology) - IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology)
Parts packaging code TSSOP - SOIC SOIC TSSOP
Contacts 16 - 16 16 16
Manufacturer packaging code PGG16 - DCG16 DCG16 PGG16
Samacsys Description TSSOP 4.4 MM 0.65MM PITCH - SOIC 150 MIL - TSSOP 4.4 MM 0.65MM PITCH
JESD-30 code R-PDSO-G16 - R-PDSO-G16 R-PDSO-G16 R-PDSO-G16
JESD-609 code e3 - e3 e3 e3
Humidity sensitivity level 1 - 3 3 1
Maximum output clock frequency 156 MHz - 156 MHz 156 MHz 156 MHz
Package body material PLASTIC/EPOXY - PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code TSSOP - SOP SOP TSSOP
Encapsulate equivalent code TSSOP16,.25 - SOP16,.25 SOP16,.25 TSSOP16,.25
Package shape RECTANGULAR - RECTANGULAR RECTANGULAR RECTANGULAR
Peak Reflow Temperature (Celsius) NOT SPECIFIED - NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
power supply 3.3/5 V - 3.3/5 V 3.3/5 V 3.3/5 V
Master clock/crystal nominal frequency 27 MHz - 27 MHz 27 MHz 27 MHz
Certification status Not Qualified - Not Qualified Not Qualified Not Qualified
Maximum seat height 1.2 mm - 1.75 mm 1.75 mm 1.2 mm
Maximum slew rate 30 mA - 30 mA 30 mA 30 mA
Maximum supply voltage 5.5 V - 5.5 V 5.5 V 5.5 V
Minimum supply voltage 3 V - 3 V 3 V 3 V
Nominal supply voltage 3.3 V - 3.3 V 3.3 V 3.3 V
surface mount YES - YES YES YES
technology CMOS - CMOS CMOS CMOS
Temperature level INDUSTRIAL - COMMERCIAL INDUSTRIAL COMMERCIAL
Terminal surface Matte Tin (Sn) - annealed - Matte Tin (Sn) - annealed Matte Tin (Sn) - annealed Matte Tin (Sn) - annealed
Terminal form GULL WING - GULL WING GULL WING GULL WING
Terminal location DUAL - DUAL DUAL DUAL
Maximum time at peak reflow temperature NOT SPECIFIED - NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
width 4.4 mm - 3.9 mm 3.9 mm 4.4 mm
uPs/uCs/peripheral integrated circuit type CLOCK GENERATOR, OTHER - CLOCK GENERATOR, OTHER CLOCK GENERATOR, OTHER CLOCK GENERATOR, OTHER
Base Number Matches 1 - 1 1 1
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