IDT71V3576S150PFI9 datasheet, PDF

Datasheet> All Categories > storage> IDT71V3576S150PFI9

IDT71V3576S150PFI9: DescriptionCache SRAM, 128KX36, 3.8ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100; Categorystorage; File Size283KB，22 Pages; ManufacturerIDT (Integrated Device Technology)

Download Datasheet Parametric View All

IDT71V3576S150PFI9 Overview

Cache SRAM, 128KX36, 3.8ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100

IDT71V3576S150PFI9 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	QFP
package instruction	LQFP,
Contacts	100
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	3.8 ns
Other features	PIPELINED ARCHITECTURE
JESD-30 code	R-PQFP-G100
JESD-609 code	e0
length	20 mm
memory density	4718592 bit
Memory IC Type	CACHE SRAM
memory width	36
Humidity sensitivity level	3
Number of functions	1
Number of terminals	100
word count	131072 words
character code	128000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	128KX36
Package body material	PLASTIC/EPOXY
encapsulated code	LQFP
Package shape	RECTANGULAR
Package form	FLATPACK, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	240
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum supply voltage (Vsup)	3.465 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	TIN LEAD
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	20
width	14 mm
Base Number Matches	1

Preview

Download Datasheet

View All

128K x 36, 256K x 18

3.3V Synchronous SRAMs

3.3V I/O, Pipelined Outputs

Burst Counter, Single Cycle Deselect

IDT71V3576S

IDT71V3578S

IDT71V3576SA

IDT71V3578SA

Features

128K x 36, 256K x 18 memory configurations

Supports high system speed:

Commercial and Industrial:

– 150MHz 3.8ns clock access time

– 133MHz 4.2ns clock access time

LBO

input selects interleaved or linear burst mode

Self-timed write cycle with global write control (GW), byte write

enable (BWE), and byte writes (BWx)

3.3V core power supply

Power down controlled by ZZ input

3.3V I/O

Optional - Boundary Scan JTAG Interface (IEEE 1149.1

compliant)

Packaged in a JEDEC Standard 100-pin plastic thin quad

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball

grid array (fBGA)

Description

The IDT71V3576/78 are high-speed SRAMs organized as

128K x 36/256K x 18. The IDT71V3576/78 SRAMs contain write, data,

address and control registers. Internal logic allows the SRAM to generate

a self-timed write based upon a decision which can be left until the end of

the write cycle.

The burst mode feature offers the highest level of performance to the

system designer, as the IDT71V3576/78 can provide four cycles of data

for a single address presented to the SRAM. An internal burst address

counter accepts the first cycle address from the processor, initiating the

access sequence. The first cycle of output data will be pipelined for one

cycle before it is available on the next rising clock edge. If burst mode

operation is selected (ADV=LOW), the subsequent three cycles of output

data will be available to the user on the next three rising clock edges. The

order of these three addresses are defined by the internal burst counter

and the

LBO

input pin.

The IDT71V3576/78 SRAMs utilize IDT’s latest high-performance

CMOS process and are packaged in a JEDEC standard 14mm x 20mm

100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array

(BGA) and a 165 fine pitch ball grid array (fBGA).

Pin Description Summary

-A

BWE

(1)

CLK

ADV

ADSC

ADSP

LBO

TMS

TDI

TCK

TDO

TRST

I/O

-I/O

, I/O

-I/O

, V

DDQ

Address Inputs

Chip Enable

Chip Selects

Output Enable

Global Write Enable

Byte Write Enable

Individual Byte Write Selects

Clock

Burst Address Advance

Address Status (Cache Controller)

Address Status (Processor)

Linear / Interleaved Burst Order

Test Mode Select

Test Data Input

Test Clock

Test Data Output

JTAG Reset (Optional)

Sleep Mode

Data Input / Output

Core Power, I/O Power

Ground

Input

Output

Input

I/O

Supply

Synchronous

Asynchronous

Synchronous

N/A

Synchronous

N/A

Synchronous

Asynchronous

Synchronous

N/A

5279 tbl 01

NOTE:

and

are not applicable for the IDT71V3578.

JUNE 2003

DSC-5279/03

Recommended Resources

Rapid design of offline 10W switching power supply

HA17385 switching power supply integrated controller internal equivalent circuit diagram

Infrared light-controlled automatic switch circuit

The three-phase electric motor is transformed into a single-phase motor with forward and reverse rotation.

Monostable delay circuit composed of a single operational amplifier

555 lantern electronic switch circuit

After the VS2005 application connects to the device, it prompts "There is no process on the other end of the pipe": I have my own platform and SDK, and the application can connect to the device, everything is normal. But when the program is running, it prompts "No process on the other end of the pipe" and then brea...; syue216 Embedded System

PB4.2 supports CF2.0 and SQL Mobile: I installed the latest patch package of wince 4.2, and DOTNETV2, DOTNETV35, and SQLMOBILE were added to the WINCE420\OTHER directory. I wanted to add some of these features to my system. So I compiled...; nanxiangzi Embedded System

USB to 232 serial port: A USB to serial port converter made with CP2102+232 chip. The driver of CP2102 is available on the Internet. Just search it. If you can't find it, leave your email address and I will send it to you....; mcu_mouse PCB Design

The running water lamp has realized the left, right, left and right, and pause functions. It still lacks the fast and low speed functions. I don’t know how to add them.: #includereg51.hsbit key1=P3^0;sbit key2=P3^1;unsigned char dat1[8]={0xfe,0xfd,0xfb,0xf7,0xef,0xdf,0xbf,0x7f};unsigned char dat2[ 8]={0x7f,0xbf,0xdf,0xef,0xf7,0xfb,0xfd,0xfe};unsigned char dat3[15]={0x...; 单片机小白啊 51mcu

JTAG debugging problem (basic problem): Hello brothers, I am currently using an emulator (banyan emulator) to debug the PXA270 development board. I still don't understand a lot about the working principle of the emulator: During the debuggi...; wanglq2005 Embedded System

Newbies ask: I need to build a conditioning circuit using analog components: to amplify the DC voltage by 1000 times, with an accuracy of about 0.2%. Please help me! Thank you...; dyqq46 Embedded System

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components