IDT72V851L15PF8 datasheet, PDF

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IDT72V851L15PF8: DescriptionFIFO, 8KX9, 10ns, Synchronous, CMOS, PQFP64, PLASTIC, TQFP-64; Categorystorage; File Size148KB，16 Pages; ManufacturerIDT (Integrated Device Technology)

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IDT72V851L15PF8 Overview

FIFO, 8KX9, 10ns, Synchronous, CMOS, PQFP64, PLASTIC, TQFP-64

IDT72V851L15PF8 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	QFP
package instruction	PLASTIC, TQFP-64
Contacts	64
Reach Compliance Code	not_compliant
ECCN code	EAR99
Maximum access time	10 ns
Maximum clock frequency (fCLK)	66.7 MHz
period time	15 ns
JESD-30 code	S-PQFP-G64
JESD-609 code	e0
length	14 mm
memory density	73728 bit
Memory IC Type	OTHER FIFO
memory width	9
Humidity sensitivity level	3
Number of functions	1
Number of terminals	64
word count	8192 words
character code	8000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	8KX9
Exportable	YES
Package body material	PLASTIC/EPOXY
encapsulated code	LQFP
Encapsulate equivalent code	QFP64,.66SQ,32
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	240
power supply	3.3 V
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum slew rate	0.04 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	20
width	14 mm
Base Number Matches	1

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3.3 VOLT DUAL CMOS SyncFIFO™

DUAL 256 X 9, DUAL 512 X 9,

DUAL 1,024 X 9, DUAL 2,048 X 9,

DUAL 4,096 X 9 , DUAL 8,192 X 9

IDT72V801

IDT72V811

IDT72V821

IDT72V831

IDT72V841

IDT72V851

.EATURES:

•

The IDT72V801 is equivalent to two IDT72V201 256 x 9 FIFOs

The IDT72V811 is equivalent to two IDT72V211 512 x 9 FIFOs

The IDT72V821 is equivalent to two IDT72V221 1,024 x 9 FIFOs

The IDT72V831 is equivalent to two IDT72V231 2,048 x 9 FIFOs

The IDT72V841 is equivalent to two IDT72V241 4,096 x 9 FIFOs

The IDT72V851 is equivalent to two IDT72V251 8,192 x 9 FIFOs

Offers optimal combination of large capacity, high speed,

design flexibility and small footprint

Ideal for prioritization, bidirectional, and width expansion

applications

10 ns read/write cycle time

5V input tolerant

Separate control lines and data lines for each FIFO

Separate Empty, Full, programmable Almost-Empty and

Almost-Full flags for each FIFO

Enable puts output data lines in high-impedance state

Space-saving 64-pin plastic Thin Quad Flat Pack (TQFP/

STQFP)

Industrial temperature range (–40°C to +85°C) is available

DESCRIPTION:

The IDT72V801/72V811/72V821/72V831/72V841/72V851/72V851 are

dual synchronous (clocked) FIFOs. The device is functionally equivalent to

two IDT72V201/72V211/72V221/72V231/72V241/72V251 FIFOs in a single

package with all associated control, data, and flag lines assigned to separate

pins.

Each of the two FIFOs (designated FIFO A and FIFO B) contained in the

IDT72V801/72V811/72V821/72V831/72V841/72V851 has a 9-bit input data

port (DA0 - DA8, DB0 - DB8) and a 9-bit output data port (QA0 - QA8,

QB0 - QB8). Each input port is controlled by a free-running clock (WCLKA,

WCLKB), and two Write Enable pins (WENA1, WENA2,

WENB1,

WENB2).

Data is written into each of the two arrays on every rising clock edge of the Write

Clock (WCLKA, WCLKB) when the appropriate Write Enable pins are

asserted.

The output port of each FIFO bank is controlled by its associated clock pin

(RCLKA, RCLKB) and two Read Enable pins (RENA1,

RENA2, RENB1,

RENB2).

The Read Clock can be tied to the Write Clock for single clock operation

or the two clocks can run asynchronous of one another for dual clock operation.

An Output Enable pin (OEA,

OEB)

is provided on the read port of each FIFO

for three-state output control.

Each of the two FIFOs has two fixed flags, Empty (EFA,

EFB)

and Full (FFA,

FFB).

Two programmable flags, Almost-Empty (PAEA,

PAEB)

and Almost-Full

(PAFA,

PAFB),

are provided for each FIFO bank to improve memory utilization.

If not programmed, the programmable flags default to Empty+7 for

PAEA

and

PAEB,

and Full-7 for

PAFA

and

PAFB.

The IDT72V801/72V811/72V821/72V831/72V841/72V851 architecture

lends itself to many flexible configurations such as:

• 2-level priority data buffering

• Bidirectional operation

• Width expansion

• Depth expansion

This FIFO is fabricated using IDT's high-performance submicron CMOS

technology.

.UNCTIONAL BLOCK DIAGRAM

WCLKA

WENA1

WENA2

WCLKB

EFA

PAEA

WENB1

PAFA

LDA

WENB2

FFA

OFFSET REGISTER

FLAG

LOGIC

RAM ARRAY

256 x 9, 512 x 9,

1,024 x 9, 2,048 x 9,

4,096 x 9, 8,192 x 9

WRITE CONTROL

LOGIC

RAM ARRAY

256 x 9, 512 x 9,

1,024 x 9, 2,048 x 9,

4,096 x 9, 8,192 x 9

- DA

- DB

LDB

INPUT REGISTER

WRITE CONTROL

LOGIC

INPUT REGISTER

OFFSET REGISTER

FLAG

LOGIC

EFB

PAEB

PAFB

FFB

WRITE POINTER

READ POINTER

READ CONTROL

LOGIC

WRITE POINTER

READ POINTER

READ CONTROL

LOGIC

OUTPUT REGISTER

RESET LOGIC

OUTPUT REGISTER

RSA

OEA

- QA

RCLKA

RENA1

RENA2

RSB

OEB

- QB

RCLKB

RENB1

RENB2

4093 drw 01

The IDT logo is a registered trademark and the SyncFIFO is a trademark of Integrated Device Technology, Inc.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES



2001 Integrated Device Technology, Inc.

APRIL 2001

DSC-4093/1

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Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

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