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IDT70V3389S5BCG

Description
Dual-Port SRAM, 64KX18, 5ns, CMOS, CBGA256, 17 X 17 MM X 1.4 MM, 1 MM PITCH, GREEN, BGA-256
Categorystorage   
File Size168KB,17 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance  
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IDT70V3389S5BCG Overview

Dual-Port SRAM, 64KX18, 5ns, CMOS, CBGA256, 17 X 17 MM X 1.4 MM, 1 MM PITCH, GREEN, BGA-256

IDT70V3389S5BCG Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeBGA
package instructionLBGA, BGA256,16X16,40
Contacts256
Reach Compliance Codecompliant
ECCN code3A991.B.2.A
Maximum access time5 ns
Other featuresPIPELINED OUTPUT MODE; SELF-TIMED WRITE CYCLE
Maximum clock frequency (fCLK)100 MHz
I/O typeCOMMON
JESD-30 codeS-CBGA-B256
JESD-609 codee1
length17 mm
memory density1179648 bit
Memory IC TypeDUAL-PORT SRAM
memory width18
Humidity sensitivity level3
Number of functions1
Number of ports2
Number of terminals256
word count65536 words
character code64000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize64KX18
Output characteristics3-STATE
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeLBGA
Encapsulate equivalent codeBGA256,16X16,40
Package shapeSQUARE
Package formGRID ARRAY, LOW PROFILE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)260
power supply2.5/3.3,3.3 V
Certification statusNot Qualified
Maximum seat height1.7 mm
Maximum standby current0.015 A
Minimum standby current3.15 V
Maximum slew rate0.36 mA
Maximum supply voltage (Vsup)3.45 V
Minimum supply voltage (Vsup)3.15 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Silver/Copper (Sn/Ag/Cu)
Terminal formBALL
Terminal pitch1 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperature30
width17 mm
Base Number Matches1
HIGH-SPEED 3.3V 64K x 18
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
Features
IDT70V3389S
True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Commercial: 4.2/5/6ns (max.)
– Industrial: 5ns (max)
Pipelined output mode
Counter enable and reset features
Dual chip enables allow for depth expansion without
additional logic
Full synchronous operation on both ports
– 7.5ns cycle time, 133MHz operation (9.6 Gbps bandwidth)
– Fast 4.2ns clock to data out
– 1.8ns setup to clock and 0.7ns hold on all control, data, and
address inputs @ 133MHz
– Data input, address, byte enable and control registers
– Self-timed write allows fast cycle time
Separate byte controls for multiplexed bus and bus
matching compatibility
LVTTL- compatible, single 3.3V (±150mV) power supply for
core
LVTTL- compatible, selectable 3.3V (±150mV)/2.5V (±125mV)
power supply for I/Os and control signals on each port
Industrial temperature range (-40°C to +85°C) is
available for selected speeds
Available in a 128-pin Thin Quad Plastic Flatpack (TQFP),
208-pin fine pitch Ball Grid Array, and 256-pin Ball
Grid Array
Green parts available, see ordering information
Functional Block Diagram
UB
L
UB
R
LB
R
R/W
R
B
W
0
L
B
W
1
L
B B
WW
1 0
R R
LB
L
R/W
L
CE
0L
CE
1L
CE
0R
CE
1R
OE
L
Dout0-8_L
Dout9-17_L
Dout0-8_R
Dout9-17_R
OE
R
64K x 18
MEMORY
ARRAY
I/O
0 L
- I/O
1 7 L
CLK
L
Din_L
Din_R
I/O
0R
- I/O
17R
CLK
R
A
15L
A
0L
CNTRST
L
ADS
L
CNTEN
L
Counter/
Address
Reg.
A
15R
ADDR_L
ADDR_R
Counter/
Address
Reg.
A
0R
CNTRST
R
ADS
R
CNTEN
R
4832 tbl 01
.
FEBRUARY 2006
1
©2006 Integrated Device Technology, Inc.
DSC 4832/11
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