Very Low Power CMOS SRAM
2M X 8 bit
Pb-Free and Green package materials are compliant to RoHS
BS62LV1600
n
FEATURES
Ÿ
Wide V
CC
operation voltage : 2.4V ~ 5.5V
Ÿ
Very low power consumption :
V
CC
= 3.0V
Operation current : 46mA (Max.) at 55ns
2mA (Max.) at 1MHz
Standby current :
1.5uA (Typ.) at 25
O
C
V
CC
= 5.0V
Operation current : 115mA (Max.) at 55ns
10mA (Max.) at 1MHz
Standby current :
6.0uA (Typ.) at 25
O
C
Ÿ
High speed access time :
-55
55ns (Max.) at V
CC
: 3.0~5.5V
-70
70ns (Max.) at V
CC
: 2.7~5.5V
Ÿ
Automatic power down when chip is deselected
Ÿ
Easy expansion with CE1, CE2 and OE options
Ÿ
Three state outputs and TTL compatible
Ÿ
Fully static operation
Ÿ
Data retention supply voltage as low as 1.5V
n
DESCRIPTION
The BS62LV1600 is a high performance, very low power CMOS
Static Random Access Memory organized as 2048K by 8 bits and
operates form a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both
high speed and low power features with typical CMOS standby
current of 1.5uA at 3.0V/25
O
C and maximum access time of 55ns at
3.0V/85
O
C.
Easy memory expansion is provided by an active LOW chip enable
(CE1), an active HIGH chip enable (CE2), and active LOW output
enable (OE) and three-state output drivers.
The BS62LV1600 has an automatic power down feature, reducing
the power consumption significantly when chip is deselected.
The BS62LV1600 is available in JEDEC standard 44-pin TSOP II
and 48-ball BGA package.
n
POWER CONSUMPTION
POWER DISSIPATION
PRODUCT
FAMILY
BS62LV1600EC
BS62LV1600FC
BS62LV1600EI
BS62LV1600FI
OPERATING
TEMPERATURE
Commercial
+0
O
C to +70
O
C
Industrial
-40
O
C to +85
O
C
STANDBY
(I
CCSB1
, Max)
Operating
(I
CC
, Max)
PKG TYPE
V
CC
=3.0V
10MHz
f
Max.
V
CC
=5.0V
V
CC
=3.0V
1MHz
V
CC
=5.0V
10MHz
f
Max.
1MHz
50uA
8.0uA
9mA
48mA
113mA
1.5mA
19mA
45mA
TSOP II-44
BGA-48-0912
100uA
16uA
10mA
50mA
115mA
2mA
20mA
46mA
TSOP II-44
BGA-48-0912
n
PIN CONFIGURATIONS
A4
A3
A2
A1
A0
CE1
NC
NC
DQ0
DQ1
VCC
VSS
DQ2
DQ3
NC
A20
WE
A19
A18
A17
A16
A15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
CE2
A8
NC
NC
DQ7
DQ6
VSS
VCC
DQ5
DQ4
NC
NC
A9
A10
A11
A12
A13
A14
n
BLOCK DIAGRAM
A20
A13
A17
A15
A18
A16
A14
A12
A7
A6
A5
A4
Address
Input
Buffer
12
Row
Decoder
4096
Memory Array
BS62LV1600EC
BS62LV1600EI
4096 x 4096
4096
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
8
Data
Input
Buffer
8
512
Column Decoder
9
Control
Address Input Buffer
8
Column I/O
Write Driver
Sense Amp
8
1
A
NC
2
OE
3
A0
4
A1
5
A2
6
CE2
Data
Output
Buffer
B
NC
NC
A3
A4
CE1
NC
C
DQ0
NC
A5
A6
NC
DQ4
D
VSS
DQ1
A17
A7
DQ5
VCC
CE1
CE2
WE
OE
V
CC
V
SS
A11 A9 A8 A3 A2 A1 A0 A10 A19
E
VCC
DQ2
NC
A16
DQ6
VSS
F
DQ3
NC
A14
A15
NC
DQ7
G
NC
A20
A12
A13
WE
NC
H
A18
A8
A9
A10
A11
A19
48-ball BGA top view
Brilliance Semiconductor, Inc.
reserves the right to change products and specifications without notice.
R0201-BS62LV1600
1
Revision 2.2
Jan.
2006
BS62LV1600
n
PIN DESCRIPTIONS
Name
A0-A20 Address Input
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
WE Write Enable Input
Function
These 21 address inputs select one of the 2048K x 8-bit in the RAM
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read form or write to the device. If either chip enable is not active, the device is
deselected and is in standby power mode. The DQ pins will be in the high impedance
state when the device is deselected.
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impendence state when OE is inactive.
There 8 bi-directional ports are used to read data from or write data into the RAM.
OE Output Enable Input
DQ0-DQ7 Data Input/Output
Ports
V
CC
V
SS
Power Supply
Ground
n
TRUTH TABLE
MODE
Not selected
(Power Down)
Output Disabled
Read
Write
CE1
H
X
L
L
L
CE2
X
L
H
H
H
WE
X
X
H
H
L
OE
X
I/O OPERATION
High Z
V
CC
CURRENT
I
CCSB
, I
CCSB1
I
CC
I
CC
I
CC
X
H
L
X
High Z
D
OUT
D
IN
n
ABSOLUTE MAXIMUM RATINGS
SYMBOL
V
TERM
T
BIAS
T
STG
P
T
I
OUT
(1)
n
OPERATING RANGE
UNITS
V
O
PARAMETER
Terminal Voltage with
Respect to GND
Temperature Under
Bias
Storage Temperature
Power Dissipation
DC Output Current
RATING
-0.5
(2)
to 7.0
-40 to +125
-60 to +150
1.0
20
RANG
Commercial
Industrial
AMBIENT
TEMPERATURE
0
O
C to + 70
O
C
-40
O
C to + 85
O
C
V
CC
2.4V ~ 5.5V
2.4V ~ 5.5V
C
C
O
W
mA
n
CAPACITANCE
(1)
(T
A
= 25 C, f = 1.0MHz)
O
SYMBOL PAMAMETER CONDITIONS MAX. UNITS
C
IN
C
IO
Input
Capacitance
Input/Output
Capacitance
V
IN
= 0V
V
I/O
= 0V
10
12
pF
pF
1. Stresses greater than those listed under ABSOLUTE
MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2.
–2.0V
in case of AC pulse width less than 30 ns.
R0201-BS62LV1600
1. This parameter is guaranteed and not 100% tested.
2
Revision 2.3
May.
2006
BS62LV1600
n
DC ELECTRICAL CHARACTERISTICS (T
A
=-40 C to +85 C)
PARAMETER
NAME
V
CC
V
IL
V
IH
I
IL
I
LO
V
OL
V
OH
I
CC
(5)
I
CC1
I
CCSB
I
CCSB1
(6)
PARAMETER
Power Supply
Input Low Voltage
Input High Voltage
Input Leakage Current
Output Leakage Current
Output Low Voltage
Output High Voltage
Operating Power Supply
Current
Operating Power Supply
Current
Standby Current
–
TTL
Standby Current
–
CMOS
V
IN
= 0V to V
CC
V
I/O
= 0V to V
CC
,
CE1= V
IH
or CE2= V
IL
, or OE = V
IH
V
CC
= Max, I
OL
= 2.0mA
V
CC
= Min, I
OH
= -1.0mA
CE1 = V
IL
and CE2 = V
IH
,
I
DQ
= 0mA, f = F
MAX(4)
CE1 = V
IL
and CE2 = V
IH
,
I
DQ
= 0mA, f = 1MHz
CE1 = V
IH
, or CE2 = V
IL
,
I
DQ
= 0mA
CE1≧V
CC
-0.2V or CE2≦0.2V,
V
IN
≧V
CC
-0.2V or V
IN
≦0.2V
V
CC
=3.0V
V
CC
=5.0V
V
CC
=3.0V
V
CC
=5.0V
V
CC
=3.0V
V
CC
=5.0V
V
CC
=3.0V
V
CC
=5.0V
O
O
TEST CONDITIONS
MIN.
2.4
-0.5
(2)
2.2
--
--
--
2.4
--
--
--
--
TYP.
(1)
--
--
--
--
--
--
--
--
--
--
1.5
6.0
MAX.
5.5
0.8
V
CC
+0.3
(3)
1
1
0.4
--
46
115
2
10
1.0
2.0
16
100
UNITS
V
V
V
uA
uA
V
V
mA
mA
mA
uA
1. Typical characteristics are at T
A
=25
O
C and not 100% tested.
2. Undershoot: -1.0V in case of pulse width less than 20 ns.
3. Overshoot: V
CC
+1.0V in case of pulse width less than 20 ns.
4. F
MAX
=1/t
RC.
5. I
CC(MAX.)
is 45mA/113mA at V
CC
=3.0V/5.0V and T
A
=70
O
C.
6. I
CCSB1(MAX.)
is 8.0uA/50uA at V
CC
=3.0V/5.0V and T
A
=70
O
C.
n
DATA RETENTION CHARACTERISTICS (T
A
= -40 C to +85 C)
SYMBOL
V
DR
I
CCDR
(3)
t
CDR
t
R
PARAMETER
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
O
O
TEST CONDITIONS
CE1≧V
CC
-0.2V or CE2≦0.2V,
V
IN
≧V
CC
-0.2V or V
IN
≦0.2V
CE1≧V
CC
-0.2V or CE2≦0.2V,
V
IN
≧V
CC
-0.2V or V
IN
≦0.2V
MIN.
1.5
--
0
TYP.
(1)
--
0.7
--
--
MAX.
--
8.0
--
--
UNITS
V
uA
ns
ns
See Retention Waveform
t
RC (2)
1. V
CC
=1.5V, T
A
=25
O
C and not 100% tested.
2. t
RC
= Read Cycle Time.
3. I
CCRD(Max.)
is 4.0uA at T
A
=70
O
C.
n
LOW V
CC
DATA RETENTION WAVEFORM (1) (CE1 Controlled)
Data Retention Mode
V
DR
≧1.5V
V
CC
V
IH
V
CC
V
CC
t
CDR
CE1≧V
CC
- 0.2V
t
R
V
IH
CE1
R0201-BS62LV1600
3
Revision 2.3
May.
2006
BS62LV1600
n
LOW V
CC
DATA RETENTION WAVEFORM (2) (CE2 Controlled)
Data Retention Mode
V
DR
≧1.5V
V
CC
V
CC
V
CC
t
CDR
t
R
CE2≦0.2V
CE2
V
IL
V
IL
n
AC TEST CONDITIONS
(Test Load and Input/Output Reference)
n
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
MUST BE
STEADY
MAY CHANGE
FROM
“H”
TO
“L”
MAY CHANGE
FROM
“L”
TO
“H”
DON’T CARE
ANY CHANGE
PERMITTED
DOES NOT
APPLY
OUTPUTS
MUST BE
STEADY
WILL BE CHANGE
FROM
“H”
TO
“L”
WILL BE CHANGE
FROM
“L”
TO
“H”
CHANGE :
STATE UNKNOW
CENTER LINE IS
HIGH INPEDANCE
“OFF”
STATE
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing
Reference Level
Output Load
t
CLZ
, t
OLZ
, t
CHZ
, t
OHZ
, t
WHZ
Others
Vcc / 0V
1V/ns
0.5Vcc
C
L
= 5pF+1TTL
C
L
= 30pF+1TTL
ALL INPUT PULSES
1 TTL
Output
C
L(1)
V
CC
GND
10%
90%
90%
10%
→ ←
Rise Time :
1V/ns
→ ←
Fall Time :
1V/ns
1. Including jig and scope capacitance.
n
AC ELECTRICAL CHARACTERISTICS (T
A
= -40 C to +85 C)
READ CYCLE
JEDEC
PARANETER
PARAMETER
NAME
NAME
DESCRIPTION
Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Chip Select to Output Low Z
Output Enable to Output Low Z
Chip Select to Output High Z
Chip Select to Output High Z
Output Enable to Output High Z
Data Hold from Address Change
(CE1)
(CE2)
(CE1)
(CE2)
(CE1)
(CE2)
CYCLE TIME : 55ns
(V
CC
=3.0~5.5V)
MIN. TYP. MAX.
55
--
--
--
--
10
10
10
--
--
--
10
--
--
--
--
--
--
--
--
--
--
--
--
--
55
55
55
25
--
--
--
30
30
25
--
CYCLE TIME : 70ns
(V
CC
= 2.7~5.5V)
MIN. TYP. MAX.
70
--
--
--
--
10
10
10
--
--
--
10
--
--
--
--
--
--
--
--
--
--
--
--
--
70
70
70
30
--
--
--
35
35
30
--
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
O
O
t
AVAX
t
AVQX
t
E1LQV
t
E2HQV
t
GLQV
t
E1LQX
t
E2HQX
t
GLQX
t
E1HQZ
t
E2LQZ
t
GHQZ
t
AVQX
t
RC
t
AA
t
ACS1
t
ACS2
t
OE
t
CLZ1
t
CLZ2
t
OLZ
t
CHZ1
t
CHZ2
t
OHZ
t
OH
R0201-BS62LV1600
4
Revision 2.3
May.
2006
BS62LV1600
n
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE 1
(1,2,4)
t
RC
ADDRESS
t
OH
D
OUT
t
AA
t
OH
READ CYCLE 2
CE1
(1,3,4)
t
ACS1
CE2
t
CLZ
D
OUT
(5)
t
ACS2
t
CHZ1
, t
CHZ2
(5)
READ CYCLE 3
(1, 4)
t
RC
ADDRESS
t
AA
OE
t
OE
CE1
(5)
t
CLZ1
t
OH
t
OLZ
t
ACS1
t
OHZ
t
CHZ1
(5)
(1,5)
CE2
(5)
t
CLZ2
t
ACS2
t
CHZ2
(1,5)
D
OUT
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE1 = V
IL
and CE2= V
IH
.
3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high.
4. OE = V
IL
.
5. Transition is measured
±
500mV from steady state with C
L
= 5pF.
The parameter is guaranteed but not 100% tested.
R0201-BS62LV1600
5
Revision 2.3
May.
2006
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