EEWORLDEEWORLDEEWORLD

Part Number

Search

531BB492M000DGR

Description
LVDS Output Clock Oscillator, 492MHz Nom, ROHS COMPLIANT, SMD, 6 PIN
Categoryoscillator   
File Size215KB,12 Pages
ManufacturerSilicon Laboratories Inc
Environmental Compliance  
Download Datasheet Parametric View All

531BB492M000DGR Overview

LVDS Output Clock Oscillator, 492MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

531BB492M000DGR Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerSilicon Laboratories Inc
Reach Compliance Codeunknown
Other featuresTAPE AND REEL
maximum descent time0.35 ns
Frequency Adjustment - MechanicalNO
frequency stability20%
JESD-609 codee4
Manufacturer's serial number531
Installation featuresSURFACE MOUNT
Nominal operating frequency492 MHz
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Oscillator typeLVDS
physical size7.0mm x 5.0mm x 1.85mm
longest rise time0.35 ns
Maximum supply voltage3.63 V
Minimum supply voltage2.97 V
Nominal supply voltage3.3 V
surface mountYES
maximum symmetry55/45 %
Terminal surfaceNickel/Gold (Ni/Au)
Base Number Matches1
S i 5 3 0 / 5 31
R
EVISION
D
C
R Y S TA L
O
S C I L L A T O R
(XO)
(10 M H
Z T O
1.4 G H
Z
)
Features
Available with any-rate output
frequencies from 10 MHz to 945 MHz
and select frequencies to 1.4 GHz
3rd generation DSPLL
®
with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
Si5602
Ordering Information:
See page 7.
Applications
SONET/SDH
Networking
SD/HD video
Test and measurement
Clock and data recovery
FPGA/ASIC clock generation
Pin Assignments:
See page 6.
(Top View)
NC
OE
GND
1
2
3
6
5
4
V
DD
Description
The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry
to provide a low jitter clock at high frequencies. The Si530/531 is available
with any-rate output frequency from 10 to 945 MHz and select frequencies to
1400 MHz. Unlike a traditional XO, where a different crystal is required for
each output frequency, the Si530/531 uses one fixed crystal to provide a
wide range of output frequencies. This IC based approach allows the crystal
resonator to provide exceptional frequency stability and reliability. In addition,
DSPLL clock synthesis provides superior supply noise rejection, simplifying
the task of generating low jitter clocks in noisy environments typically found in
communication systems. The Si530/531 IC based XO is factory configurable
for a wide variety of user specifications including frequency, supply voltage,
output format, and temperature stability. Specific configurations are factory
programmed at time of shipment, thereby eliminating long lead times
associated with custom oscillators.
®
CLK–
CLK+
Si530 (LVDS/LVPECL/CML)
OE
NC
GND
1
2
3
6
5
4
V
DD
Functional Block Diagram
V
DD
CLK– CLK+
NC
CLK
Si530 (CMOS)
Fixed
Frequency
XO
Any-rate
10–1400 MHz
DSPLL
®
Clock
Synthesis
OE
NC
GND
1
2
3
6
5
4
V
DD
CLK–
CLK+
Si531 (LVDS/LVPECL/CML)
OE
GND
Rev. 1.1 6/07
Copyright © 2007 by Silicon Laboratories
Si530/531
Essential for competitions - dual-channel analog-to-digital conversion synchronous display circuit
[i=s]This post was last edited by paulhyde on 2014-9-15 08:58[/i] Must-have for competition - dual-channel analog-to-digital conversion synchronous display circuit. If you find it useful, please downl...
czs308 Electronics Design Contest
Why does this affect the analog signal?
I am making a GUI board with steering detection. The video signal is an analog signal. However, when turning, the square wave signal generated by the car will affect the board and the video will be di...
liuzhiying666 PCB Design
AD5791 schematic (99se)
AD5791 schematic diagram (99se) Continuing ADI DIY activities and Renesas DIY activities [[i] This post was last edited by Lan Yuye on 2013-11-9 13:04 [/i]]...
蓝雨夜 ADI Reference Circuit
Misunderstandings and Countermeasures in Microcontroller System Design
Misunderstandings and Countermeasures in Microcontroller System Design...
青城山下 MCU
Verilog HDL statements can be synthesized experience
Synthesis of continuous assignment statements: Extract logic from the right side of the assignment statement to drive the net procedure on the left side of the assignment statement Synthesis of assign...
eeleader-mcu FPGA/CPLD
Electronic Connector Contact Resistance Test Procedure
前言﹕本通讯第23期曾介绍EIA规范有关低阶接触阻抗测试(TP-23A)﹐主要适用于传输讯号用的連接器。本期所介绍接触[url=http://article.ednchina.com/word/162364.aspx]电阻[/url]测试则适用于传输电力之連接器﹐所  通之电流高出甚多﹐为主要相異之处。  1.0TP-06A接触电阻  2.0目的  本[url=http://article.edn...
clj2004000 Test/Measurement

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 889  1660  432  1449  1147  18  34  9  30  24 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号