531SB665M000DG datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > oscillator> 531SB665M000DG

531SB665M000DG: DescriptionLVDS Output Clock Oscillator, 665MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; Categoryoscillator; File Size215KB，12 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

531SB665M000DG Overview

LVDS Output Clock Oscillator, 665MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

531SB665M000DG Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
package instruction	ROHS COMPLIANT, SMD, 6 PIN
Reach Compliance Code	unknown
Other features	TRAY
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	20%
JESD-609 code	e4
Manufacturer's serial number	531
Installation features	SURFACE MOUNT
Nominal operating frequency	665 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	LVDS
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	0.35 ns
Maximum supply voltage	2.75 V
Minimum supply voltage	2.25 V
Nominal supply voltage	2.5 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)
Base Number Matches	1

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

EVISION

R Y S TA L

S C I L L A T O R

(XO)

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH

Networking

SD/HD video

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.1 6/07

Si530/531

Recommended Resources

LOGO! Control circuit b

Synchronous motor thyristor excitation circuit 2

Application examples of LM381f

Thyristor voltage stabilizing device circuit

Simple charger circuit

810 computer motherboard circuit diagram_01

About the limitations of in-depth study of switching power supplies!!!: At first, I was engaged in low-power mobile phone chargers, and later I made a 30W switching power supply at most. I never had the opportunity to go to a switching power supply factory to really pract...; gh131413 Power technology

How to call the soft input panel: I use evc to write a wince program and call the soft input panel function SHSipPreference(this->m_hWnd,SIP_UP); but it reports an error: error C2065: 'SHSipPreference' : undeclared identifier error C2...; vashaoye Embedded System

MAX7219 cascade driver problem: I'm working on a project recently, 51 control digital tubes, the chip used is MAX7219 cascade mode, 9 cascade drive 69 digital tubes (8 chips drive full 8 bits, one chip only drives 5 bits), there are...; 鑫海宝贝 Integrated technical exchanges

How to calculate power saving based on power factor?: I would like to ask you, the 250W high pressure sodium lamp street light used to have no compensation (power factor was 0.5), the stable current was 3.8A, now after compensation the power factor becom...; nhsl Industrial Control Electronics

[Qinheng RISC-V core CH582] 4-The mobile phone reads and writes data from CH582: Use the CH582 development board as the GATT server to provide data read and write operations. In this way, you can establish a connection with it through a mobile phone and perform read and write oper...; manhuami2007 Domestic Chip Exchange

EEWORLD University Hall ---- Operating System Principles Tian Lihua, Xi'an Jiaotong University: Principles of Operating Systems Tian Lihua, Xi'an Jiaotong University : https://training.eeworld.com.cn/course/5839The course of operating system principles mainly introduces the design methods and im...; 木犯001号 MCU

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

Popular Components