EEWORLDEEWORLDEEWORLD

Part Number

Search

531SB693M000DGR

Description
LVDS Output Clock Oscillator, 693MHz Nom, ROHS COMPLIANT, SMD, 6 PIN
Categoryoscillator   
File Size215KB,12 Pages
ManufacturerSilicon Laboratories Inc
Environmental Compliance  
Download Datasheet Parametric View All

531SB693M000DGR Overview

LVDS Output Clock Oscillator, 693MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

531SB693M000DGR Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerSilicon Laboratories Inc
package instructionROHS COMPLIANT, SMD, 6 PIN
Reach Compliance Codeunknown
Other featuresTAPE AND REEL
maximum descent time0.35 ns
Frequency Adjustment - MechanicalNO
frequency stability20%
JESD-609 codee4
Manufacturer's serial number531
Installation featuresSURFACE MOUNT
Nominal operating frequency693 MHz
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Oscillator typeLVDS
physical size7.0mm x 5.0mm x 1.85mm
longest rise time0.35 ns
Maximum supply voltage2.75 V
Minimum supply voltage2.25 V
Nominal supply voltage2.5 V
surface mountYES
maximum symmetry55/45 %
Terminal surfaceNickel/Gold (Ni/Au)
Base Number Matches1
S i 5 3 0 / 5 31
R
EVISION
D
C
R Y S TA L
O
S C I L L A T O R
(XO)
(10 M H
Z T O
1.4 G H
Z
)
Features
Available with any-rate output
frequencies from 10 MHz to 945 MHz
and select frequencies to 1.4 GHz
3rd generation DSPLL
®
with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
Si5602
Ordering Information:
See page 7.
Applications
SONET/SDH
Networking
SD/HD video
Test and measurement
Clock and data recovery
FPGA/ASIC clock generation
Pin Assignments:
See page 6.
(Top View)
NC
OE
GND
1
2
3
6
5
4
V
DD
Description
The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry
to provide a low jitter clock at high frequencies. The Si530/531 is available
with any-rate output frequency from 10 to 945 MHz and select frequencies to
1400 MHz. Unlike a traditional XO, where a different crystal is required for
each output frequency, the Si530/531 uses one fixed crystal to provide a
wide range of output frequencies. This IC based approach allows the crystal
resonator to provide exceptional frequency stability and reliability. In addition,
DSPLL clock synthesis provides superior supply noise rejection, simplifying
the task of generating low jitter clocks in noisy environments typically found in
communication systems. The Si530/531 IC based XO is factory configurable
for a wide variety of user specifications including frequency, supply voltage,
output format, and temperature stability. Specific configurations are factory
programmed at time of shipment, thereby eliminating long lead times
associated with custom oscillators.
®
CLK–
CLK+
Si530 (LVDS/LVPECL/CML)
OE
NC
GND
1
2
3
6
5
4
V
DD
Functional Block Diagram
V
DD
CLK– CLK+
NC
CLK
Si530 (CMOS)
Fixed
Frequency
XO
Any-rate
10–1400 MHz
DSPLL
®
Clock
Synthesis
OE
NC
GND
1
2
3
6
5
4
V
DD
CLK–
CLK+
Si531 (LVDS/LVPECL/CML)
OE
GND
Rev. 1.1 6/07
Copyright © 2007 by Silicon Laboratories
Si530/531
[Transfer] High-speed PCB design: Common clock system timing example
In the previous topic, we introduced the timing principle of the common clock bus. This topic will use an example to illustrate. A single board is a standard CPCI architecture, and the chips used are ...
wstt PCB Design
CS5463 based on 51 single chip microcomputer
There are still some problems with the measurement accuracy and adjustment of the results of CS5463, but it can be used successfully! ! #include "stc15f2k60s2.h" #include #define uchar unsigned char #...
lxxcj6 51mcu
Google Wave
Media reports on April 1. [b][/b] Google said that when there is a new message in the Google Wave inbox, the system will send a real person to notify the user....
天天谈芯 Talking
MSP430F5438 Study Notes UART ACLK 9600-8-N-1
1. Before initializing UART0, you need to initialize ACLK, SMCLK and MCLK. In the sample code, XT1 is used, ACLK is 32768, and SMCLK and MCLK are about 8MHZ. 2. The clock of UART can refer to ACLK or ...
fish001 Microcontroller MCU
Newbie help, about the problem of brushless drive
I am currently participating in a school competition on electronic design. The topic is to control the speed of a DC motor (5V~12V) to 10000rpm~20000rpm. I currently only have a 2212 model aircraft br...
xieer Electronics Design Contest
[TI's first low-power design competition] Copter_alarm_powered_by_MSP430FR5969 six LED display and PCB
LED display and PCB physical object Software module detailed design begins 4-bit 7-segment LED dynamic display tasks and heartbeat tasks are completed Picture 179141 [/attach] [/align ... [media=x,500...
tziang Microcontroller MCU

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 1949  917  1778  694  758  40  19  36  14  16 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号