74FCT163373APAG datasheet, PDF

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74FCT163373APAG: DescriptionTSSOP-48, Tube; Categorylogic; File Size204KB，8 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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74FCT163373APAG Overview

TSSOP-48, Tube

74FCT163373APAG Parametric

Parameter Name	Attribute value
Brand Name	Integrated Device Technology
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	TSSOP
package instruction	TSSOP, TSSOP48,.3,20
Contacts	48
Manufacturer packaging code	PAG48
Reach Compliance Code	compliant
ECCN code	EAR99
Samacsys Description	TSSOP 6.1 MM 0.5MM PITCH
Other features	MAX O/P SKEW = 0.5NS; TYP VOLP = 0.3V
series	FCT
JESD-30 code	R-PDSO-G48
JESD-609 code	e3
length	12.5 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	BUS DRIVER
MaximumI(ol)	0.024 A
Humidity sensitivity level	1
Number of digits	8
Number of functions	2
Number of ports	2
Number of terminals	48
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output characteristics	3-STATE
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Encapsulate equivalent code	TSSOP48,.3,20
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packing	TUBE
Peak Reflow Temperature (Celsius)	260
power supply	3/3.3 V
Prop。Delay @ Nom-Sup	5.2 ns
propagation delay (tpd)	8.5 ns
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	2.7 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Matte Tin (Sn) - annealed
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	6.1 mm
Base Number Matches	1

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IDT74FCT163373A/C

3.3V CMOS 16-BIT TRANSPARENT LATCH

INDUSTRIAL TEMPERATURE RANGE

3.3V CMOS 16-BIT

TRANSPARENT LATCH

IDT74FCT163373A/C

FEATURES:

• 0.5 MICRON CMOS Technology

• Typical t

SK(o)

(Output Skew) < 250ps

• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using

machine model (C = 200pF, R = 0)

• V

= 3.3V ± 0.3V, Normal Range, or V

= 2.7V to 3.6V, Extended

Range

• CMOS power levels (0.4μ W typ. static)

• Rail-to-rail output swing for increased noise margin

• Low Ground Bounce (0.3V typ.)

• Inputs (except I/O) can be driven by 3.3V or 5V components

• Available in SSOP and TSSOP packages

DESCRIPTION:

The FCT163373 16-bit transparent D-type latches are built using

advanced dual metal CMOS technology. These high-speed, low-power

latches are ideal for temporary storage of data. They can be used for

implementing memory address latches, I/O ports, and bus drivers. The

Output Enable and Latch Enable controls are organized to operate each

device as two 8-bit latches or one 16-bit latch. Flow-through organization

of signal pins simplifies layout. All inputs are designed with hysteresis for

improved noise margin.

The inputs of FCT163373 can be driven from either 3.3V or 5V devices.

This feature allows the use of these transparent latches as translators in a

mixed 3.3V/5V supply system. With xLE inputs high, the FCT163373 can

be used as a buffer to connect 5V components to a 3.3V bus.

FUNCTIONAL BLOCK DIAGRAM

TO SEVEN OTHER CHANNELS

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

INDUSTRIAL TEMPERATURE RANGE

SEPTEMBER 2009

DSC-5416/6

74FCT163373APAG Related Products

	74FCT163373APAG	74FCT163373CPVG8	74FCT163373CPVG
Description	TSSOP-48, Tube	SSOP-48, Reel	SSOP-48, Tube
Brand Name	Integrated Device Technology	Integrated Device Technology	Integrated Device Technology
Is it lead-free?	Lead free	Lead free	Lead free
Is it Rohs certified?	conform to	conform to	conform to
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
Parts packaging code	TSSOP	SSOP	SSOP
package instruction	TSSOP, TSSOP48,.3,20	SSOP, SSOP48,.4	SSOP, SSOP48,.4
Contacts	48	48	48
Manufacturer packaging code	PAG48	PVG48	PVG48
Reach Compliance Code	compliant	compliant	compliant
ECCN code	EAR99	EAR99	EAR99
Samacsys Description	TSSOP 6.1 MM 0.5MM PITCH	SSOP 300 MIL	SSOP 300 MIL
Other features	MAX O/P SKEW = 0.5NS; TYP VOLP = 0.3V	MAX O/P SKEW = 0.5NS; TYP VOLP = 0.3V	MAX O/P SKEW = 0.5NS; TYP VOLP = 0.3V
series	FCT	FCT	FCT
JESD-30 code	R-PDSO-G48	R-PDSO-G48	R-PDSO-G48
JESD-609 code	e3	e3	e3
length	12.5 mm	15.875 mm	15.875 mm
Load capacitance (CL)	50 pF	50 pF	50 pF
Logic integrated circuit type	BUS DRIVER	BUS DRIVER	BUS DRIVER
MaximumI(ol)	0.024 A	0.024 A	0.024 A
Humidity sensitivity level	1	1	1
Number of digits	8	8	8
Number of functions	2	2	2
Number of ports	2	2	2
Number of terminals	48	48	48
Maximum operating temperature	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C
Output characteristics	3-STATE	3-STATE	3-STATE
Output polarity	TRUE	TRUE	TRUE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSSOP	SSOP	SSOP
Encapsulate equivalent code	TSSOP48,.3,20	SSOP48,.4	SSOP48,.4
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE, SHRINK PITCH
method of packing	TUBE	TAPE AND REEL	TUBE
Peak Reflow Temperature (Celsius)	260	260	260
power supply	3/3.3 V	3/3.3 V	3/3.3 V
Prop。Delay @ Nom-Sup	5.2 ns	4.2 ns	4.2 ns
propagation delay (tpd)	8.5 ns	5.5 ns	5.5 ns
Certification status	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.2 mm	2.794 mm	2.794 mm
Maximum supply voltage (Vsup)	3.6 V	3.6 V	3.6 V
Minimum supply voltage (Vsup)	2.7 V	2.7 V	2.7 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES
technology	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal surface	Matte Tin (Sn) - annealed	Matte Tin (Sn) - annealed	Matte Tin (Sn) - annealed
Terminal form	GULL WING	GULL WING	GULL WING
Terminal pitch	0.5 mm	0.635 mm	0.635 mm
Terminal location	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	30	30	30
width	6.1 mm	7.5 mm	7.5 mm

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