FUJITSU SEMICONDUCTOR
DATA SHEET
DS04-22114-1E
Communication Control
ASSP
IP PACKET FORWARDING ENGINE
MB86977
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DESCRIPTION
The MB86977 is an LSI that enables processes that previously were handled through software, such as packet-
destination transferring and filtering, to be handled through hardware, thereby achieving a full wire speed bi-
directional LAN-WAN throughput of 100 Mbps. The IP forwarding can be applied to both IPv4 and IPv6 packets
at full wire speed.The Layer 3/4 filtering capabilities enables application of basic security policies, and also makes
it possible to build Demilitarized Zones (D.M.Z.) for servers to be accessed directly from the WWW without
intervention of software. Out of a total of four MAC interfaces, two are used for internal segments (i.e. LAN0,LAN1),
one as a D.M.Z. port, and the remaining as a WAN port. The D.M.Z.interface may be configured as an extra
internal segment (i.e. LAN2)if desired. The Layer 2 switch can switch packets from internal segments (LAN0,
LAN1 and LAN2) based on their MAC addresses.
In addition, real-time applications such as streaming media flows and VoIP streams can be prioritized by the
priority control function. The MB86977 offers the ideal solution for superior performance required by network
appliances such as broadband routers.
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FEATURES
1. Built-in high performance IP Forwarding Engine “Fujitsu/FLS Express Forwarding (FEF)”
Engine
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IP packet forwarding
• Routing operations such as Ethernet MAC Address replacement, TTL reduction and checksum generation done
in hardware
• Supports both IPv4 and IPv6
• Supports PPPoE Tunneling and IPv6 over IPv4 Tunneling at WAN Interface
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PACKAGE
208-pin plastic LQFP
(FPT-208P-M06)
MB86977
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NAT (NAPT)
• NAT operations such as IP Address replacement, Transport layer port number replacement, and checksum
generation done in hardware
• Supports PPPoE Tunneling and IPv6 over IPv4 Tunneling at WAN Interface
• Supports IPv4 only.
•
Layer 3/4 Filtering
• Filtering based on IP Address (Dst and/or Src, supports both IPv4/IPv6)
• Filtering based on TCP/UDP port number (supports TCP and ACK flag)
• Filtering based on combinations of IP address and TCP port number in TCP connections for both IPv4 and IPv6.
• Filtering based on ICMP Type
• Filtering based on Protocol Type (Type field in Ethernet)
• Supports PPPoE discovery stage /session stage filtering
• Supports AH (Authentication Header) Type VPN packet filtering by Layer 3/4 information
• Supports ESP (Encapsulating Security Payload) type VPN packets filtering by IP Address
• Filtering can be applied independently per each port (LAN,D.M.Z., WAN)
• Supports Max 64x2 (Inbound and Outbound) Filter Table Entries
• Supports filter logging
•
Packet Prioritizing Function
• Prioritization based on combination of IPv4 address and UDP port number
• Prioritization based on combination of IPv4 address and ToS field
• Prioritization based on combination of IPv4 address, ToS field and UDP port number
• Prioritization based on combination of IPv6 address, Traffic Class and Flow Label
• Supports QoS mapping ToS field
Note: The FEF supports only DIX type Ethernet Frames, and does not support IEEE802.1 LLC type frames and
IEEE802.1Q VLAN tagged frames (These frames, when received, will be sent to the host).
Achieving a full wire rate bi-directional throughput of 100 Mbps at 50 MHz operation.
2. Layer 2 (MAC) Functions
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Four integrated IEEE802.3 compliant 10/100BaseT/TX MAC ports
Port selectable RMII/MII interface (Supports both full duplex and half duplex)
SMI Interface for PHY device configuration
Supports Auto Negotiation
Supports IEEE802.3x Flow control
Supports back pressure for half duplex mode
Integrated SRAM for packet buffering (PRAM)
Store-and-Forward switching method
MAC Address table up to 50 entries
MAC Address auto learning and aging
3. Host Interface
• 32 bit-width SRAM host interface
• BigEndian/LittleEndian configurable
4. Other features
• 208-pin Plastic LQFP Package
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MB86977
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PIN DESCRIPTION
•
Host (SRAM) interface
Pin No.
Pin Name
173 to 184
15 to 25
29 to 38
42 to 52
166
167
168
8
A2 to A13
I/O
I
ADDRESS BUS
Address input
DATA INPUT/OUTPUT
Data input/output (32 bit)
CHIP SELECT
Chip select input
WRITE ENABLE
Write operation enable signal (low enable)
READ ENABLE
Read operation enable signal (low enable)
INTERRUPT
Interrupt indication (low enable)
Function
DQ0 to DQ31
I/O
CS_
WE_
RE_
INT_
I
I
I
O
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RMII interface
Pin No.
164
150, 151
108, 109
60, 61
102, 103
149
107
59
101
141
127
79
93
137, 138
123, 124
75, 76
89, 90
132
118
70
84
Pin Name
REF_CLK
TXD_W [1 : 0]
TXD_D [1 : 0]
TXD_0 [1 : 0]
TXD_1 [1 : 0]
TX_EN_W
TX_EN_D
TX_EN_0
TX_EN_1
RX_ER_W
RX_ER_D
RX_ER_0
RX_ER_1
RXD_W [1 : 0]
RXD_D [1 : 0]
RXD_0 [1 : 0]
RXD_1 [1 : 0]
CRS_DV_W
CRS_DV_D
CRS_DV_0
CRS_DV_1
I/O
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Function
REFERENCE CLOCK
Reference clock from the PHY device.
The frequency is 50 MHz for both 10 Mbps and 100 Mbps.
TRANSMIT DATA
The two bit data is transmitted to PHY devices through this
interface. Synchronous with REF_CLK.
TRANSMIT ENABLE
Active high signal indicates that TX data is valid.Synchronous with
REF_CLK.
RECEIVE ERROR
Active high signal indicates that an invalid symbol has been
detected within a received packet.This input is ignored when the
CRS_DV signal is inactive.
RECEIVE DATA
The two bit data is received from the PHY device through this
interface.
CARRIER SENSE / RECEIVE DATA VALID
PHY Device inputs active high signal when the interface is
receiving data. Asynchronous assertion/deassertion by PHY
device upon carrier detection/carrier invalid.
O
O
I
I
I
Note : The logical AND of the TX_EN and CRS_DV signals indicate a collision during half duplex modes.
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