5962-9458505HTX datasheet, PDF

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5962-9458505HTX: DescriptionEEPROM Module, 128KX32, 140ns, Parallel, CMOS, HIP-66; Categorystorage; File Size380KB，43 Pages; ManufacturerWhite Microelectronics

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5962-9458505HTX Overview

EEPROM Module, 128KX32, 140ns, Parallel, CMOS, HIP-66

5962-9458505HTX Parametric

Parameter Name	Attribute value
Maker	White Microelectronics
package instruction	HIP-66
Reach Compliance Code	unknown
Maximum access time	140 ns
Other features	USER CONFIGURABLE AS 512K X 8
Spare memory width	16
JESD-30 code	S-XHIP-P66
length	30.1 mm
memory density	4194304 bit
Memory IC Type	EEPROM MODULE
memory width	32
Number of functions	1
Number of terminals	66
word count	131072 words
character code	128000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	128KX32
Package body material	UNSPECIFIED
encapsulated code	HIP
Package shape	SQUARE
Package form	IN-LINE
Parallel/Serial	PARALLEL
Programming voltage	5 V
Certification status	Not Qualified
Maximum seat height	6.22 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	MILITARY
Terminal form	PIN/PEG
Terminal pitch	2.54 mm
Terminal location	HEX
width	30.1 mm
Maximum write cycle time (tWC)	10 ms
Base Number Matches	1

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REVISIONS

LTR

DESCRIPTION

Added device type 06 for vendor cages 54230 and 88379. Added

vendor cage 0EU86 for device types 01 through 06. Figure 1,

changed case outline M to reflect package is available in either a

single or dual cavity. -sld

Added case outline 9.

Added device types 07, 08, and 09 for vendor cage 0EU86. Made

changes to table I to include the addition of device types 07, 08, and

09. Added a min limit to the table I for the I

, and the I

tests. Made

changes to Figures 2, 3, 4, 5, 6, and 8. -sld

Added case outline Z. Updated paragraph 1.2.4, 1.3, figures 1, 2,

and 8. -sld

Added case outline B. Added note to paragraph 1.2.4. -sld

DATE (YR-MO-DA)

99-05-14

APPROVED

K. A. Cottongim

00-04-06

02-01-31

Raymond Monnin

02-06-04

03-10-06

Raymond Monnin

REV

SHEET

REV

SHEET

REV STATUS

OF SHEETS

PMIC N/A

REV

SHEET

PREPARED BY

Gary Zahn

CHECKED BY

Michael C. Jones

STANDARD

MICROCIRCUIT

DRAWING

THIS DRAWING IS

AVAILABLE

FOR USE BY ALL

DEPARTMENTS

AND AGENCIES OF THE

DEPARTMENT OF DEFENSE

AMSC N/A

DEFENSE SUPPLY CENTER COLUMBUS

POST OFFICE BOX 3990

COLUMBUS, OHIO 43216-5000

APPROVED BY

Kendall A. Cottongim

MICROCIRCUIT, HYBRID, MEMORY,

DIGITAL, 128K x 32-BIT, ELECTRICALLY

ERASABLE/PROGRAMMABLE READ ONLY

MEMORY

SIZE

SHEET

CAGE CODE

DRAWING APPROVAL DATE

94-08-02

REVISION LEVEL

67268

1 OF

5962-94585

DSCC FORM 2233

APR 97

DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.

5962-E009-04

2. APPLICABLE DOCUMENTS

2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a

part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those listed in

the issue of the Department of Defense Index of Specifications and Standards (DoDISS) and supplement thereto, cited in the

solicitation.

SPECIFICATION

DEPARTMENT OF DEFENSE

MIL-PRF-38534 - Hybrid Microcircuits, General Specification for.

STANDARDS

DEPARTMENT OF DEFENSE

MIL-STD-883 - Test Method Standard Microcircuits.

MIL-STD-1835 - Interface Standard Electronic Component Case Outlines.

HANDBOOKS

DEPARTMENT OF DEFENSE

MIL-HDBK-103 - List of Standard Microcircuit Drawings.

MIL-HDBK-780 - Standard Microcircuit Drawings.

(Unless otherwise indicated, copies of the specification, standards, and handbooks are available from the Standardization

Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)

2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text

of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a

specific exemption has been obtained.

3. REQUIREMENTS

3.1 Item requirements. The individual item performance requirements for device classes D, E, G, H, and K shall be in

accordance with MIL-PRF-38534. Compliance with MIL-PRF-38534 may include the performance of all tests herein or as

designated in the device manufacturer's Quality Management (QM) plan or as designated for the applicable device class.

Therefore, the tests and inspections herein may not be performed for the applicable device class (see MIL-PRF-38534).

Furthermore, the manufacturers may take exceptions or use alternate methods to the tests and inspections herein and not

perform them. However, the performance requirements as defined in MIL-PRF-38534 shall be met for the applicable device

class.

3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified

in MIL-PRF-38534 and herein.

3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein and figure 1.

3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2.

3.2.3 Truth table(s). The truth table(s) shall be as specified on figure 3.

3.2.4 Timing diagram(s). The timing diagram(s) shall be as specified on figures 4, 5, 6, and 7.

3.2.5 Block diagram. The block diagram shall be as specified on figure 8.

3.2.5 Typical output test circuit. The typical output test circuit shall be as specified on figure 9.

3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are

as specified in table I and shall apply over the full specified operating temperature range.

STANDARD

MICROCIRCUIT DRAWING

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 43216-5000

SIZE

REVISION LEVEL

5962-94585

SHEET

DSCC FORM 2234

APR 97

3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical

tests for each subgroup are described in table I.

3.5 Programming procedure. The programming procedure shall be as specified by manufacturer and shall be available on

request.

3.6 Marking of device(s). Marking of device(s) shall be in accordance with MIL-PRF-38534. The device shall be marked with

the PIN listed in 1.2 herein. In addition, the manufacturer's vendor similar PIN may also be marked as listed in MIL-HDBK-103

and QML-38534.

3.7 Data. In addition to the general performance requirements of MIL-PRF-38534, the manufacturer of the device described

herein shall maintain the electrical test data (variables format) from the initial quality conformance inspection group A lot

sample, for each device type listed herein. Also, the data should include a summary of all parameters manually tested, and for

those which, if any, are guaranteed. This data shall be maintained under document revision level control by the manufacturer

and be made available to the preparing activity (DSCC-VA) upon request.

3.8 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to supply to this

drawing. The certificate of compliance (original copy) submitted to DSCC-VA shall affirm that the manufacturer's product meets

the performance requirements of MIL-PRF-38534 and herein.

3.9 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38534 shall be provided with each lot of

microcircuits delivered to this drawing.

3.10 Endurance. A reprogrammability test shall be completed as part of the vendor's reliability monitors. This

reprogrammability test shall be done for the initial characterization and after any design or process changes which may affect

the reprogrammability of the device. The methods and procedures may be vendor specific, but shall guarantee the number of

program/erase endurance cycles listed in section 1.3 herein over the full specified operating temperature range. The vendor's

procedure shall be kept under document control and shall be made available upon request of the acquiring or preparing activity.

3.11 Data retention. A data retention stress test shall be completed as part of the vendor's reliability monitors. This test shall

be done for initial characterization and after any design or process change which may affect data retention. The methods and

procedures may be vendor specific, but shall guarantee the number of years listed in section 1.3 herein over the full military

temperature range. The vendor's procedure shall be kept under document control and shall be made available upon request of

the acquiring or preparing activity.

STANDARD

MICROCIRCUIT DRAWING

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 43216-5000

SIZE

REVISION LEVEL

5962-94585

SHEET

DSCC FORM 2234

APR 97

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