PRELIMINARY DATA SHEET
MICRONAS
INTERMETALL
DDP 3300 A
Single-Chip Display
and Deflection
Processor
Edition June 19, 1996
6251-421-1PD
DDP 3300 A
Contents
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Section
1.
1.1.
1.2.
1.3.
1.3.1.
1.3.2.
1.3.3.
2.
2.1.
2.1.1.
2.1.2.
2.1.3.
2.1.4.
2.1.5.
2.1.6.
2.1.7.
2.1.8.
2.1.9.
2.1.10.
2.1.11.
2.1.12.
2.1.13.
2.1.14.
2.1.15.
2.1.16.
2.2.
2.2.1.
2.2.2.
2.2.3.
2.3.
2.3.1.
2.3.2.
2.3.3.
2.3.4.
2.3.5.
2.4.
2.4.1.
2.4.2.
2.4.3.
2.4.4.
3.
3.1.
3.2.
Title
Introduction
System Architecture
DDP Applications
Digital Video Interfaces
Picture Bus Interface
Digital OSD Interface
Priority Interface
Functional Description
Display Part
Luma Input
Luma Contrast Adjustment
Black Level Expander
Dynamic Peaking
Digital Brightness Adjustment
Soft Limiter
Chroma Input
Chroma Interpolation
Chroma Transient Improvement
Inverse Matrix
RGB Processing
OSD Color Lookup Table
Picture Frame Generator
Priority Codec
Scan Velocity Modulation
Display Phase Shifter
Analog Back End
CRT Measurement and Control
SCART Output Signal
Average Beam Current Limiter
Synchronization and Deflection
Deflection Processing
Horizontal Phase Adjustment
Vertical and East/West Deflection
Protection Circuitry
Deflection Bus
Reset and Standby Functions
Standby Mode for VPC and DDP
DDP Power on
DDP Standby On/Off
Reset DDP
Serial Interface
I
2
C-bus Interface
Control and Status Registers
PRELIMINARY DATA SHEET
2
MICRONAS INTERMETALL
PRELIMINARY DATA SHEET
DDP 3300 A
Contents,
continued
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Section
4.
4.1.
4.2.
4.3.
4.4.
4.5.
4.6.
4.6.1.
4.6.2.
4.6.3.
4.6.4.
4.6.5.
4.6.6.
4.6.7.
4.6.8.
4.6.9.
4.6.10.
4.6.11.
4.6.12.
4.6.13.
4.6.14.
4.6.15.
4.6.16.
4.6.17.
4.6.18.
4.6.19.
4.6.20.
4.6.21.
4.6.22.
4.6.23.
5.
Title
Specifications
Outline Dimensions
Pin Connections and Short Descriptions
Pin Descriptions (Pin Numbers for PLCC68)
Pin Configuration
Pin Circuits
Electrical Characteristics
Absolute Maximum Ratings
Recommended Operating Conditions
Characteristics
General Characteristics
Bus Inputs: Luma, Chroma, OSD, Front Sync
20.25 MHz Main Clock Input, internally AC coupled
5 MHz Clock Input
I
2
C-Bus Interface
Reset Input, Test Input
Serial Deflection Interface
Priority Bus Input
Horizontal Flyback Input
Main Sync Output
Combined Sync Output
Horizontal Drive Output
Vertical Protection Input
Vertical Safety Input
Vertical and East/West Drive Output
Sense A/D Converter Input
Analog RGB and FB Inputs
Analog RGB Outputs, D/A Converters
DAC Reference, Beam Current Safety
Scan Velocity Modulation Output
Data Sheet History
MICRONAS INTERMETALL
3
DDP 3300 A
DDP 3300 A, Display and Deflection Processor
50/60 Hz
(68-pin PLCC or 64-pin PSDIP Package)
Note:
Revision bars indicate significant changes to the pre-
vious version, ed. 6251-421-1AI, Advance Information,
dated Feb. 9, 1996.
1. Introduction
The DDP 3300 A is a single-chip digital display and
deflection processor in 0.8
µm
CMOS technology for
high quality back-end applications in 50/60 Hz TV sets
with 4:3 or 16:9 picture tubes. It can be combined with
members of the DIGIT 3000 IC family (VPC 3200 A,
VPC 3201 B, TPU 3040) or it can be used with third par-
ty products. One IC contains the entire video component
and deflection processing and forms the heart of a mod-
ern color TV. Its performance and complexity allow the
user to standardize his product development. Hardware
and software applications can profit from the modularity,
as well as manufacturing, system support or mainte-
nance. The main features are
– single 5 V power supply
– low cost, high performance all digital video processing
– black-level expander
– dynamic peaking
– soft limiter (gamma correction)
PRELIMINARY DATA SHEET
– color transient improvement
– programmable RGB matrix
– scan velocity modulation output
– picture frame generator
– additional analog RGB/fastblank input
– Prio interface
– various digital interfaces
– high performance H/V deflection
– separate ADC for tube measurements
1.1. System Architecture
Open architecture is the key word to the new DSP gener-
ation. Flexible standard building blocks have been de-
fined that offer continuity and transparency of the entire
system. Two main modules were defined:
– Video Processor and
– Display and Deflection Processor.
They were designed as separate ICs. Their partitioning
permits a variety of IC configurations with the aim to sat-
isfy the particular requirements of different applications.
Both, analog and digital interfaces, support state-of-the
art TV receivers as well as other environments. Fig. 1–1
shows the block diagram of the single-chip Display and
Deflection Processor.
scan
vel.
mod.
3 x DAC
(10 bit)
and
tube
control
SVM
YCrCb
4:2:2
RGB
Prio
FPDAT
Y features
C features
digital
RGB
matrix
color
lookup
table
dig.
RGB
switch
analog
RGB
switch
RGB
out
RGB/
Fbl
in
H/V deflection
DACs
I
2
C
interface
measu-
rement
ADC
Hflyb.
Hdrive
V & E/W
timing generator
SDA, SCL
main
sync
front
sync
range
switch
1&2
sense
input
Fig. 1–1:
Display and Deflection Processor
4
MICRONAS INTERMETALL
PRELIMINARY DATA SHEET
DDP 3300 A
separation for PAL and NTSC and all of their substan-
dards. Both versions of the VPC are plug-in compatible.
The CIP 3250 A provides a high-quality analog RGB in-
terface with character insertion capability. This allows
appropriate processing of external sources such as
MPEG2 set-top boxes in transparent (4:2:2) quality. Fur-
thermore, it translates RGB/Fastblank signals to the
common digital video bus and makes those signals
available for 100 Hz processing. In some European
countries (Italy), this feature is mandatory.
The IP indicates memory based image processing, such
as scan rate conversion, vertical processing (Zoom), or
PAL+ reconstruction.
Examples:
– Europe: 15 kHz /50 Hz
→
32 kHz /100 Hz interlaced
– US: 15 kHz /60 Hz
→
31 kHz /60 Hz non-interlaced
Note that the VPC supports memory based applications
through line-locked clocks, syncs, and data. CIP may
run either with the native DIGIT3000 clock but also with
a line-locked clock system.
1.2. DDP Applications
Fig. 1–2 depicts several DDP applications. Since the
DDP functions as a video back-end, it must be
complemented with additional functionality to form a
complete TV set.
The DDP 3310 B will be a further development of the
DDP 3300 A. It is targeted for a system with a horizontal
frequency of 32 kHz and a vertical frequency of 100 or
120 Hz.
The VPC3210A/3211B processes all worldwide analog
video signals (including the European PALplus) and al-
lows nonlinear Panorama aspect ratio conversion. Thus
4:3 and 16:9 systems can easily be configured by soft-
ware. The aspect ratio scaling is also used as a sample
rate converter to provide a line-locked digital component
output bus (YCrCb) compliant to ITUR–601. All video
processing and line-locked clock/data generation is
derived from a single 20.25 MHz crystal. An optional
adaptive 2-line combfilter (VPC3211B) performs Y/C
RGB saturation
Scan Vel. Mod.
Fastbl. mixing
Combfilter
16:9 Video
CVBS
RGB
VPC
320X
DDP
3300A
RGB
H/V
Defl.
n
n
n
CVBS
RGB
VPC
321X
CIP
3250A
IP
DDP
3310B
RGB
H/V
Defl.
n
n
n
n
n
PAL+
100 Hz
Fig. 1–2:
DDP 3300 A Applications
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