Ordering number : EN6000
Monolithic Linear IC
LV4124W
Single-chip LCD panel driver IC
(Supports the ALP202 LCD panel)
Overview
The LV4124W is a LCD panel driver for use in low-
temperature polysilicon TFT LCDs that integrates an RGB
decoder, a driver, and a timing controller in a single chip.
This IC is manufactured in Bi-CMOS process and
supports the ALP202 2.0-inch color LCD panel.
Package Dimensions
unit: mm
SQFP-64
[LV4124W]
Functions
• Analog block: RGB decoder/driver
• Digital block: Timing generator
Features
•
•
•
•
•
•
•
Supports NTSC/PAL standard
Supports composite, Y/C, and Y/color difference inputs
Built-in BPF, TRAP, and DL circuits
Sharpness function
Dual point
γ
correction circuit
Pre-charge circuit
R and B outputs delay time correction circuit
(Supports up and down and right and left inversions)
• Polarity reverse circuit
• External RGB input supported
• Line inversion supported
• Supports AC drive for the LCD panel during no signal
• Serial bus for mode setting and electric VR
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SANYO: SQFP64
Package
• SQFP-64 plastic package
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
82198RM (OT) No.6000-1/21
LV4124W
Specifications
Maximum Ratings
at Ta = 25°C
Parameter
Symbol
V
CC
1 max
Maximum supply voltage
V
CC
2 max
V
DD
max
Allowable power dissipation
Operating temperature
Storage temperature
Input pin voltage
Pd max
Topr
Tstg
VINA
VIND
Analog input pins
Digital input pins
Conditions
Analog 4.5V system
Analog 12V system
Digital system
With Ta
≤
75°C*
Rating
6
14
4.5
350
–15 to +75
–40 to +125
–0.3 to V
CC
1
–0.3 to V
DD
+0.3
Units
V
V
V
mV
°C
°C
V
V
Note
*:
When mounted on a printed circuit board (30
×
30 mm, t = 1.6 mm, material: glass/epoxy)
Operating Conditions
at Ta = 25°C
Parameter
Symbol
V
CC
1
Recommended supply voltage
V
CC
2
V
DD
V
CC
1op
Operating supply voltage range
V
CC
2op
V
DD
op
Conditions
Analog 4.5V system
Analog 12V system
Digital system
Analog 4.5V system
Analog 12V system
Digital system
Rating
4.5
12.0
3.0
4.25 to 5.25
11 to 13.5
2.7 to 3.6
Units
V
V
V
V
V
V
Electrical Characteristics
at V
CC
1 = 4.5 V, V
CC
2 = V
CC
PCD = 12.0 V, GND1 = GND2 = GNDPCD = 0 V, V
DD
=
3.0 V V
SS
1 = V
SS
2 = 0 V, and Ta = 25°C
DC Characteristics
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Parameter
[Current Characteristics]
Symbol
Conditions
Ratings
min
typ
max
Unit
ICC11
Current drain: V
CC
1
4.5V system
ICC12
ICC13
Current drain: V
CC
2
12V system
Current drain: V
DD
MOS circuit blocks
Input SIG4 to (A) and SIG2 (0 dB) to (B).
Measure the ICC1 current.
Input SIG4 to (A), (D), and (E).
Measure the ICC1 current.
Input SIG4 to (A) and SIG2 (0 dB) to (B).
Measure the ICC2 current.
Input SIG4 to (A) and SIG2 (0 dB) to (B).
Measure the IDD current.
Composite input
Y/C input
Y/color difference
input
22
21
18
29
28
23
35
34
28
mA
mA
mA
ICC2
4.5
6.5
8.5
mA
IDD
4.5
6.0
7.5
mA
[Digital Block Input and Output Characteristics]
Input current
High-level output voltage
Low-level output voltage
CKO pin high-level output voltage
CKO pin low-level output voltage
RPD pin high-level output voltage
RPD pin low-level output voltage
RPD pin output off leakage current
Input voltage threshold (high)
Input voltage threshold (low)
II1
II2
V
OH
1
V
OL
1
V
OH
2
V
OL
2
V
OH
3
V
OL
3
IOFF
VTDH
VTDL
Input pins with built-in pull-up resistors
*
1
Input pins with built-in pull-down resistors
Ioh = –1 mA
*
3
Iol = 1 mA
*
3
Ioh = –3 mA
Iol = 3 mA
Ioh = –0.5 mA
Ioh = 0.7 mA
In the high-impedance state, V
OUT
= V
SS
or V
DD
.
Input pins
*
1
,
*
2
Input pins
*
1
,
*
2
–40
0.7V
DD
0.3V
DD
V
DD
– 1.2
1.0
40
0.5V
DD
0.5V
DD
*
2
V
IN
= V
SS
V
IN
= V
DD
–24
24
V
DD
– 0.2
0.3
–60
60
–145
145
µA
µA
V
V
V
V
V
V
µA
V
V
Notes: 1. Input pins with built-in pull-up resistors: VDIN, CSH, CSV, SCLK, DATA, and LOAD
2. Input pins with built-in pull-down resistors: PANEL and TEST
3. Output pins other than CKO and RPD: XSTH, STH, CKH2, CKH1, PCG2, PCG1, HD, XSTV, STV, CKV2, CKV1, XENB, ENB, and VD.
No.6000-2/21
LV4124W
AC Characteristics (1)
when the T41, T44, and T46 outputs are measured at the noninverted outputs.
Parameter
[Luminance Signal System]
Contrast characteristics (typ.)
GCNTTP
Input SIG4 to (A) and measure the ratio of the T44 output
amplitude (white - black) to the input amplitude.
Input SIG4 to (A) and measure the ratio of the T44 output
amplitude (white - black) to the input amplitude.
Input SIG4 to (A) and measure the ratio of the T44 output
amplitude (white - black) to the input amplitude.
13
17
21
dB
Symbol
Conditions
Ratings
min
typ
max
Unit
Contrast characteristics (min.)
GCNTMN
–9
–5
–1
dB
Maximum video gain
GV
19
22
25
dB
[Luminance Signal Frequency Characteristics]
Y/C input
FCYYC
Take the T44 output amplitude with SIG7 (0 dB, no burst,
100 kHz) input to (A) as 0 dB. Modify the input frequency
and determine the frequency such that the output is down
–3 dB.
5.0
NTSC
Composite input
PAL
FCYCMN
2.5
MHz
FCYCMP
2.5
GSHP1X
Image quality adjustment
range 1 (Y/C input)
GSHP1N
Take the T44 output amplitude with SIG7
(100 kHz) input to (A) as 0 dB. Determine
the ratio of the output amplitude with a
2.5-MHz SIG7 input.
MAX
12
16
dB
MIN
0
2
GSHP3X
Image quality adjustment
range 3 (composite input)
GSHP3N
Take the T44 output amplitude with SIG7
(100 kHz) input to (A) as 0 dB. Determine the
ratio of the output amplitude with a 2.0-MHz
SIG7 input.
MAX
6
10
dB
MIN
–2
3
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Chrominance signal leakage
CRLEKY
Input SIG2 (0 dB) to (A) and using a spectrum analyzer,
measure the 3.58 and 4.43 MHz components in the input and
in T44. Let
∆CLK
be that difference. Use that value to
determine CRLEKY from the following formula:
CRLEKY
= 150 mV
×
10
∆CLK/20
30
mV
[Luminance Signal Input to Output Delay]
Y/C input
NTSC
Composite input
PAL
[Color Difference Signal System]
TDYCMP
TDYYC
TDYCMN
Input SIG5 (VL = 150 mV) to (A).Measure the delay time
between a rising edge in the input and the corresponding
rising edge in the T44 noninverted output.
250
500
500
350
600
600
450
700
700
ns
ns
ns
GEXCMX
Color difference input color
adjustment
GEXCMN
Input SIG5 (VL = 150 mV) to (A) and SIG1 (0 dB, 100 kHz,
no burst) to (D). Let VC0 be the T41 output amplitude
(100 kHz) when COL = 128. Let VC2 be the T41 output
amplitude (100 kHz) when COL = 0. Let VC1 be the T41
output amplitude (100 kHz) when SIG1 is set to -10 dB and
COL = 255. Then calculate the following formulas.
GEXCMX = 20log (VC1/VC0) +10
GEXCMN = 20log (VC2/VC0)
+4
+6
dB
–15
–11
dB
Color difference balance
VEXCBL
Input SIG5 (VL = 150 mV) to (A) and SIG1 (0 dB, 100 kHz,
no burst) to (D) and (E).
Let VB be the T41 output amplitude (100 kHz), and let VR
be the T46 output amplitude (100 kHz).
Calculate VEXCBL = VR/VB.
0.85
1
1.15
–
Continued on next page.
No.6000-3/21
LV4124W
Continued from preceding page
Parameter
[Color Difference Signal System]
GEXRMX
Color difference input balance
adjustment R
GEXRMN
Input SIG5 (VL = 150 mV) to (A) and SIG1 (–6 dB, 100 kHz,
no burst) to (D) and (E).
When TINT = 128, let VR0 be the T46 output amplitude
(100 kHz) and let VB0 be the T41 output amplitude (100 kHz).
When TINT = 255, let VR1 be the T46 output amplitude and
let VB1 be the T41 output amplitude.
When TINT = 0, let VR2 be the T46 output amplitude and let
VB2 be the T41 output amplitude.
Then calculate the following formulas.
GEXRMX = 20log (VR1/VR0) GEXRMN = 20log (VR2/VR0)
GEXBMX = 20log (VB1/VB0) GEXBMN = 20log (VB2/VB0)
Input SIG5 (VL = 150 mV) to (A) and SIG1 (0 dB, 100 kHz,
no burst) to (D).
Let VEXB be the T41 output amplitude (100 kHz) and
VEXBG be the T44 output amplitude (100 kHz).Calculate
VEXGB = VEXBG/VEXB.
Input SIG5 (VL = 150 mV) to (A) and SIG1 (0 dB, 100 kHz,
no burst) to (E).
Let VEXR be the T46 output amplitude (100 kHz) and
VEXRG be the T44 output amplitude (100 kHz).
Calculate VEXGR = VEXRG/VEXR.
Input SIG5 (VL = 150 mV) to (A) and SIG1 (0 dB, 100 kHz,
no burst) to (D).
Let VEXB be the T41 output amplitude (100 kHz) and
VEXBG be the T44 output amplitude (100 kHz).Calculate
VEXGB = VEXBG/VEXB.
Input SIG5 (VL = 150 mV) to (A) and SIG1 (0 dB, 100 kHz,
no burst) to (E).
Let VEXR be the T46 output amplitude (100 kHz) and
VEXRG be the T44 output amplitude (100 kHz).
Calculate VEXGR = VEXRG/VEXR.
+2
+3
dB
Symbol
Conditions
Ratings
min
typ
max
Unit
–3
–4.5
dB
GEXBMX
Color difference input balance
adjustment B
GEXBMN
–3
–4.5
dB
+2
+3
dB
VEXGBN
G-Y matrix characteristics
(NTSC)
VEXGRN
0.21
0.24
0.27
–
0.46
0.51
0.56
–
VEXGRP
G-Y matrix characteristics
(PAL)
VEXGRP
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0.17
0.19
0.21
–
0.46
0.51
0.56
–
AC Characteristics (2)
Parameter
[Chrominance Signal System]
Input SIG5 (VL = 150 mV) to (A), and to (B),
input SIG2 (0, +6, and –20 dB, 3.58 MHz,
burst/chrominance phase = 180°, and also
4.43 MHz, burst/chrominance phase = ±135°).
Measure the T53 output amplitude, and let V0,
V1, and V2 correspond to 0 dB, +6 dB, and
–20 dB, respectively.
ACC1 = 20log (V1/V0)
ACC2 = 20log (V2/V0)
Input SIG5 (VL = 150 mV) to (A), and to (B),
input SIG2 (0 dB, 3.58 MHz, burst/chrominance
phase = 180°, and also 4.43 MHz,
burst/chrominance phase = ±135°).
Measure the T44 output amplitude. Modify the
SIG2 burst frequency, until the killer is
released. Measure the frequency f1 that
appears in the T41 output.
NTSC f1 = 3579545 Hz
PAL
f1 = 4433619 Hz
NTSC
–3
0
+3
Symbol
Conditions
Ratings
min
typ
max
Unit
ACC amplitude characteristics 1
ACC1
PAL
–3
0
+3
dB
VTSC
–3
0
+3
ACC amplitude characteristics 2
ACC2
PAL
–3
0
+3
NTSC
±500
APC pull-in range
FAPC
Hz
PAL
±500
Continued on next page.
No.6000-4/21
LV4124W
Continued from preceding page
Parameter
[Chrominance Signal System]
Color adjustment
characteristics (maximum)
Input SIG5 (VL = 150 mV) to (A), and input SIG2 (0 dB,
burst/chrominance phase = 180°) to (B).
Let V0, V1, and V2 be the chrominance signal amplitude
when COL = 128, COL = 255, and COL = 0, respectively.
Calculate GCOLMX = 20log (V1/V0), and GCOLMN = 20log
(V2/V0).
Symbol
Conditions
Ratings
min
typ
max
Unit
GCOLMX
+4
+6
dB
Color adjustment
characteristics (minimum)
GCOLMN
–20
–15
dB
Tint adjustment range
(maximum)
TNTMX
Tint adjustment range
(minimum)
TNTMN
Input SIG5 (VL = 150 mV) to (A), and input SIG2 (0 dB, with
a variable burst/chrominance phase) to (B).
Let
θ
0,
θ
1, and
θ
2 be the phases when the T41 output
amplitude is minimum when TINT = 128, TINT = 255, and
TINT = 0, respectively.
Calculate TNTMX =
θ1
–
θ0,
and TNTMN =
θ2
–
θ0.
–30
–40
deg
30
40
deg
ACKN
Killer operating input level
ACKP
Input SIG5 (VL = 150 mV) to (A), and to (B),
input SIG2 (with a variable level,
burst/chrominance phase = 180°, and also
burst/chrominance phase = ±135°).
Measure the T41 output amplitude.
Gradually lower the SIG3 level (amplitude) until
the killer function operates and measure that
level.
NTSC
–36
30
dB
PAL
–33
–27
dB
VRBN
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Demodulator output
amplitude ratio (NTSC)
VGBN
Input SIG5 (VL = 150 mV) to (A), and input SIG3 (0 dB) to
(B).
Modify the chrominance signal phase, let VB be the
maximum amplitude of the T41 chrominance demodulated
signal, let VG be the maximum amplitude of the T44
chrominance demodulated signal, and let VR be the
maximum amplitude of the T46 chrominance demodulated
signal
Calculate VRBN = VR/VB and VGBN = VG/VB.
Input SIG5 (VL = 150 mV) to (A), and input SIG3 (0 dB) to
(B).
Modify the chrominance signal phase, let
θ
B be the phase
at the maximum amplitude of the T41 chrominance
demodulated signal, let
θ
G be the phase at the maximum
amplitude of the T44 chrominance demodulated signal, and
let
θ
R be the phase at the maximum amplitude of the T46
chrominance demodulated signal.
Calculate
θ
RBN =
θ
R –
θ
B and
θ
GBN =
θ
G –
θ
B.
Input SIG5 (VL = 150 mV) to (A), and input SIG3 (0 dB) to
(B).
Modify the chrominance signal phase, let VB be the
maximum amplitude of the T41 chrominance demodulated
signal, let VG be the maximum amplitude of the T44
chrominance demodulated signal, and let VR be the
maximum amplitude of the T46 chrominance demodulated
signal
Calculate VRBP = VR/VB and VGBP = VG/VB.
Input SIG5 (VL = 150 mV) to (A), and input SIG3 (0 dB) to
(B).
Modify the chrominance signal phase, let
θ
B be the phase
at the maximum amplitude of the T41 chrominance
demodulated signal, let
θ
G be the phase at the maximum
amplitude of the T44 chrominance demodulated signal, and
let
θ
R be the phase at the maximum amplitude of the T46
chrominance demodulated signal.
Calculate
θ
RBP =
θ
R –
θ
B and
θ
GBP =
θ
G –
θ
B.
0.53
0.63
0.73
–
0.25
0.32
0.39
–
θ
RBN
Demodulator output phase
difference (NTSC)
θ
GBN
99
109
119
deg
230
242
254
deg
VRBP
Demodulator output
amplitude ratio (PAL)
VGBP
0.65
0.75
0.85
–
0.33
0.40
0.47
–
θ
RBP
Demodulator output phase
difference (PAL)
θ
GBP
80
90
100
deg
232
244
256
deg
No.6000-5/21
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