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5962-8994803MNC

Description
Field Programmable Gate Array, 2000 Gates, 100MHz, 64-Cell, CMOS, CQFP100, QFP-100
CategoryProgrammable logic   
File Size53KB,8 Pages
ManufacturerXILINX
Websitehttps://www.xilinx.com/
Download Datasheet Parametric View All

5962-8994803MNC Overview

Field Programmable Gate Array, 2000 Gates, 100MHz, 64-Cell, CMOS, CQFP100, QFP-100

5962-8994803MNC Parametric

Parameter NameAttribute value
MakerXILINX
Parts packaging codeQFP
package instructionGQFF, TPAK100,2.6SQ,25
Contacts100
Reach Compliance Codeunknown
ECCN code3A001.A.2.C
maximum clock frequency100 MHz
Combined latency of CLB-Max7 ns
JESD-30 codeS-CQFP-F100
JESD-609 codee4
length19.05 mm
Equivalent number of gates2000
Number of entries64
Number of logical units64
Output times64
Number of terminals100
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
organize2000 GATES
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeGQFF
Encapsulate equivalent codeTPAK100,2.6SQ,25
Package shapeSQUARE
Package formFLATPACK, GUARD RING
power supply5 V
Programmable logic typeFIELD PROGRAMMABLE GATE ARRAY
Certification statusNot Qualified
Filter levelMIL-STD-883
Maximum seat height3.2258 mm
Maximum supply voltage5.5 V
Minimum supply voltage4.5 V
Nominal supply voltage5 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal surfaceGOLD
Terminal formFLAT
Terminal pitch0.635 mm
Terminal locationQUAD
width19.05 mm
Base Number Matches1
®
All new designs should use XC3000A.
Information on XC3000 is presented here
as a reference for existing designs.
XC3000 bitstreams are upward compatible
to XC3000A without modification.
IMPORTANT NOTICE
XC3000
Logic Cell Array Family
Product Specification
Features
Description
XC3000 is the original family of devices in the XC3000
class of Field Programmable Gate Array (FPGA) architec-
tures. The XC3000 family has a proven track record in
addressing a wide range of design applications, including
general logic replacement and sub-systems integration.
For a thorough description of the XC3000 architecture see
the preceding pages of this data book.
The XC3000 Family covers a range of nominal device
densities from 2,000 to 9,000 gates, practically achievable
densities from 1,000 to 6,000 gates. Device speeds,
described in terms of maximum guaranteed toggle fre-
quencies, range from 70 to 125 MHz. The performance of
a completed design depends upon placement and routing
implementation, so, like with any gate array, the final
verification of device utilization and performance can only
be known after the design has been placed and routed.
Industry-leading FPGA family with five device types
– Logic densities from 1,000 to 6,000 gates
– Up to 144 user-definable I/Os
Guaranteed 70- to 125-MHz toggle rates, 9 to 5.5 ns
logic delays
Advanced CMOS static memory technology
– Low quiescent and active power consumption
XC3000-specific features
– Ultra-low current option in Power-Down mode
– 4-mA output sink and source current
– Broad range of package options includes plastic and
ceramic quad flat packs, plastic leaded chip carriers
and pin grid arrays
– 100% bitstream compatible with the XC3100 family
– Commercial, industrial, military, “high rel”, and MIL-
STD-883 Class B grade devices
– Easy migration to XC3300 series of HardWire mask-
programmed devices for high-volume production
Device
XC3020
XC3030
XC3042
XC3064
XC3090
CLBs
64
100
144
224
320
Array
8x8
10 x 10
12 x 12
16 x 14
16 x 20
User I/Os
Max
64
80
96
120
144
Flip-Flops
256
360
480
688
928
Horizontal
Longlines
16
20
24
32
40
Configuration
Data Bits
14,779
22,176
30,784
46,064
64,160
2-153
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