P89V52X2
8-bit 80C51 low power 8 kB flash microcontroller with 256 B
RAM, 192 B data EEPROM
Rev. 01 — 7 June 2007
Preliminary data sheet
1. General description
The P89V52X2 is an 80C51 microcontroller with 8 kB flash, 256 B of data RAM, and
192 B of data EEPROM. This device is designed to be a drop in and software compatible
replacement for the P87C52, P87C52X2, P89C52, and P89C52X2 devices.
2. Features
2.1 Principal features
0 MHz to 33 MHz operating frequency in 12× mode, 20 MHz in 6× mode
8 kB of on-chip flash user code memory
256 B of RAM
Enhanced UART
Three 16-bit timers/counters
Four 8-bit I/O ports
Supports 12-clock (default) or 6-clock mode selection via software or In-Circuit
Programming (ICP)
DIP40, PLCC44, and LQFP44 packages
Six interrupt sources with four priority levels
Second DPTR register
2.2 Additional features
Low EMI mode (ALE inhibit)
Power-down mode with external interrupt wake-up
Idle mode
Extended temperature range
Three security bits
Programmable clock-out pin
NXP Semiconductors
P89V52X2
80C51 with 256 B RAM, 192 B data EEPROM
3. Ordering information
Table 1.
Ordering information
Package
Name
P89V52X2FN
P89V52X2FBD
P89V52X2FA
DIP40
LQFP44
PLCC44
Description
plastic dual in-line package; 40 leads (600 mil) SOT129-1
plastic low profile quad flat package; 44 leads; SOT389-1
body 10
×
10
×
1.4 mm
plastic leaded chip carrier; 44 leads
SOT187-2
Version
Type number
4. Block diagram
P89V52X2
HIGH PERFORMANCE 80C51 CPU
8 kB
CODE FLASH
256 B
DATA RAM
UART
internal
bus
TIMER 0
TIMER 1
TXD
RXD
T0
T1
T2
T2EX
P3[7:0]
PORT 3
TIMER 2
P2[7:0]
X1
PORT 2
PORT 1
P1[7:0]
CRYSTAL
OR
RESONATOR
OSCILLATOR
X2
PORT 0
P0[7:0]
002aac565
Fig 1. Block diagram
P89V52X2_1
© NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 01 — 7 June 2007
2 of 56
NXP Semiconductors
P89V52X2
80C51 with 256 B RAM, 192 B data EEPROM
5. Pinning information
5.1 Pinning
P1.0/T2
P1.1/T2EX
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
1
2
3
4
5
6
7
8
9
40 V
CC
39 P0.0/AD0
38 P0.1/AD1
37 P0.2/AD2
36 P0.3/AD3
35 P0.4/AD4
34 P0.5/AD5
33 P0.6/AD6
32 P0.7/AD7
31 EA
30 ALE
29 PSEN
28 P2.7/A15
27 P2.6/A14
26 P2.5/A13
25 P2.4/A12
24 P2.3/A11
23 P2.2/A10
22 P2.1/A9
21 P2.0/A8
002aac564
P3.0/RXD 10
P3.1/TXD 11
P3.2/INT0 12
P3.3/INT1 13
P3.4/T0 14
P3.5/T1 15
P3.6/WR 16
P3.7/RD 17
XTAL2 18
XTAL1 19
V
SS
20
P89V52X2
Fig 2. DIP40 pin configuration
P89V52X2_1
© NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 01 — 7 June 2007
3 of 56
NXP Semiconductors
P89V52X2
80C51 with 256 B RAM, 192 B data EEPROM
P1.1/T2EX
43 P0.0/AD0
42 P0.1/AD1
41 P0.2/AD2
P1.5
P1.6
P1.7
7
8
9
40 P0.3/AD3
39 P0.4/AD4
38 P0.5/AD5
37 P0.6/AD6
36 P0.7/AD7
35 EA
34 n.c.
33 ALE
32 PSEN
31 P2.7/A15
30 P2.6/A14
29 P2.5/A13
P2.4/A12 28
34 P0.3/AD3
33 P0.4/AD4
32 P0.5/AD5
31 P0.6/AD6
30 P0.7/AD7
29 EA
28 n.c.
27 ALE
26 PSEN
25 P2.7/A15
24 P2.6/A14
23 P2.5/A13
P2.4/A12 22
002aac562
002aac563
P1.0/T2
2
V
SS
22
P1.4
P1.3
P1.2
RST 10
P3.0/RXD 11
n.c. 12
P3.1/TXD 13
P3.2/INT0 14
P3.3/INT1 15
P3.4/T0 16
P3.5/T1 17
P3.6/WR 18
P3.7/RD 19
XTAL2 20
XTAL1 21
n.c. 23
P2.0/A8 24
P2.1/A9 25
37 P0.0/AD0
P2.1/A9 19
P2.2/A10 26
36 P0.1/AD1
P2.2/A10 20
P2.3/A11 27
P2.3/A11 21
35 P0.2/AD2
P89V52X2
Fig 3. PLCC44 pin configuration
41 P1.1/T2EX
40 P1.0/T2
V
SS
16
42 P1.2
44 P1.4
43 P1.3
P1.5
P1.6
P1.7
RST
P3.0/RXD
n.c.
P3.1/TXD
P3.2/INT0
P3.3/INT1
1
2
3
4
5
6
7
8
9
P89V52X2
P3.4/T0 10
P3.5/T1 11
P3.6/WR 12
P3.7/RD 13
XTAL2 14
XTAL1 15
n.c. 17
P2.0/A8 18
Fig 4. LQFP44 pin configuration
P89V52X2_1
38 V
DD
39 n.c.
44 V
DD
6
5
4
3
1
n.c.
© NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 01 — 7 June 2007
4 of 56
NXP Semiconductors
P89V52X2
80C51 with 256 B RAM, 192 B data EEPROM
5.2 Pin description
Table 2.
Symbol
P0.0 to P0.7
Pin description
Pin
DIP40
LQFP44
PLCC44
I/O
Port 0:
Port 0 is an 8-bit open-drain bidirectional I/O port.
Port 0 pins that have ‘1’s written to them float, and in this
state can be used as high-impedance inputs. Port 0 is also
the multiplexed low-order address and data bus during
accesses to external code and data memory. In this
application, it uses strong internal pull-ups when
transitioning to ‘1’s. External pull-ups are required as a
general purpose I/O port.
P0.0 —
Port 0 bit 0.
AD0 —
Address/data bit 0.
P0.1 —
Port 0 bit 1.
AD1 —
Address/data bit 1.
P0.2 —
Port 0 bit 2.
AD2 —
Address/data bit 2.
P0.3 —
Port 0 bit 3.
AD3 —
Address/data bit 3.
P0.4 —
Port 0 bit 4.
AD4 —
Address/data bit 4.
P0.5 —
Port 0 bit 5.
AD5 —
Address/data bit 5.
P0.6 —
Port 0 bit 6.
AD6 —
Address/data bit 6.
P0.7 —
Port 0 bit 7.
AD7 —
Address/data bit 7.
Port 1:
Port 1 is an 8-bit bidirectional I/O port with internal
pull-ups. The Port 1 pins are pulled high by the internal
pull-ups when ‘1’s are written to them and can be used as
inputs in this state. As inputs, Port 1 pins that are
externally pulled LOW will source current (I
IL
) because of
the internal pull-ups. P1.5, P1.6, P1.7 have high current
drive of 16 mA.
P1.0 —
Port 1 bit 0.
T2 —
External count input to Timer/Counter 2 or Clock-out
from Timer/Counter 2
P1.1 —
Port 1 bit 1.
T2EX:
Timer/Counter 2 capture/reload trigger and
direction control
P1.2 —
Port 1 bit 2.
P1.3 —
Port 1 bit 3.
P1.4 —
Port 1 bit 4.
P1.5 —
Port 1 bit 5.
P1.6 —
Port 1 bit 6.
© NXP B.V. 2007. All rights reserved.
Type
Description
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
P1.0 to P1.7
39
38
37
36
35
34
33
32
37
36
35
34
33
32
31
30
43
42
41
40
39
38
37
36
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O with
internal
pull-up
P1.0/T2
1
40
2
I/O
I
P1.1/T2EX
2
41
3
I/O
I
P1.2
P1.3
P1.4
P1.5
P1.6
P89V52X2_1
3
4
5
6
7
42
43
44
1
2
4
5
6
7
8
I/O
I/O
I/O
I/O
I/O
Preliminary data sheet
Rev. 01 — 7 June 2007
5 of 56
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