Twos Complement, Dual 12-Bit DAC
with Internal REF and Fast Settling Time
AD5399
FEATURES
2-channel 12-bit DAC
Twos complement facilitates bipolar applications
Bipolar zero with 2 V dc offset
Built-in 2.000 V precision reference with 10 ppm/°C typ TC
Buffered voltage output: 0 V to 4 V
Single-supply operation: 4.5 V to 5.5 V
Fast 0.8 µs settling time typ
Ultracompact MSOP-10 package
Monotonic DNL < ±1 LSB
Optimized accuracy at zero scale
Power-on reset to V
REF
3-wire serial data input
Extended temperature range: –40°C to +105°C
V
TP
V
DD
FUNCTIONAL BLOCK DIAGRAM
AD5399
×2
X2
V
REF
2V
×2
V
OUTB
V
BZ
– 2V = 0V
V
BZ
(V
REF
) = 2V
V
OUTA
V
BZ
+ 2V = 4V
AGND
DECODER SW
DRIVER A
12
DECODER SW
DRIVER B
12
DAC B
REGISTER
12
POWER-ON
RESET
03469-B-001
CS
CLK
SDI
DGND
EN
ADDR
DECODE
A0
16-BIT
D15...D0
DAC A
REGISTER
APPLICATIONS
Single-supply bipolar converter operations
General-purpose DSP applications
Digital gain and offset controls
Instrumentation level settings
Disk drive control
Precision motor control
Figure 1.
V
OUT
= ((D – 2048)/4096 × 4 V) + 2 V for 0 ≤
D
≤ 4095, where
D
is the decimal code.
Table 1. Examples of Twos Complement Codes
Twos Complement
2047
2046
1
0
4095
2049
2048
4.0
3.5
3.0
V
OUT
= [(0 – 2048)/4096 × 4V] + 2V
2.5
GENERAL DESCRIPTION
The AD5399 is the industry-first dual 12-bit digital-to-analog
converter that accepts twos complement digital coding with 2 V
dc offset for single-supply operation. Augmented with a built-in
precision reference and a solid buffer amplifier, the AD5399 is
the smallest self-contained 12-bit precision DAC that fits many
general-purpose as well as DSP specific applications. The twos
complement programming facilitates the natural coding
implementation commonly found in DSP applications, and
allows operation in single supply. The AD5399 provides a 2 V
reference output, V
REF
, for bipolar zero monitoring. It can also
be used for other on-board components that require a precision
reference. The device is specified for operation from 5 V ± 10%
single supply with bipolar output swing from 0 V to 4 V
centered at 2 V.
The AD5399 is available in the compact 1.1 mm low profile
MSOP-10 package. All parts are guaranteed to operate over the
extended industrial temperature range of –40°C to +105°C.
D
4095
4094
2049
2048
2047
1
0
Scale
+FS
+FS – 1 LSB
BZS + 1 LSB
BZS
BZS – 1 LSB
–FS + 1 LSB
–FS
V
OUT
(V)
4.000
3.999
2.001
2.000
1.999
0.001
0.000
FS = Full Scale, BZS = Bipolar Zero Scale.
V
OUT
(V)
2.0
1.5
1.0
0.5
0
03469-B-002
0
512
1024
1536
2048
2560
3072
TWOS COMPLEMENT CODE
3584
4096
Figure 2. Output vs. Twos Complement Code
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2004 Analog Devices, Inc. All rights reserved.
AD5399
TABLE OF CONTENTS
Specifications..................................................................................... 3
Electrical Characteristics ............................................................. 3
Absolute Maximum Ratings............................................................ 4
ESD Caution.................................................................................. 4
Pin Configuration and Function Descriptions............................. 5
Timing Characteristics..................................................................... 6
Typical Performance Characteristics ..............................................7
Operation......................................................................................... 10
Power-Up/Power-Down Sequence .......................................... 10
Outline Dimensions ....................................................................... 12
Ordering Guide .......................................................................... 12
REVISION HISTORY
6/04—Data sheet changed from Rev. C to Rev. D
Correction to Table 7 Caption ...................................................... 11
3/04—Data sheet changed from Rev. B to Rev. C
Changes to Specifications ................................................................ 3
Changes to Table 4............................................................................ 5
Replaced Figures 4 and 5 ................................................................. 6
Changes to Operation Section ...................................................... 10
Changes to Table 6.......................................................................... 10
11/03—Data sheet changed from Rev. A to Rev. B
Changes to Table 5 notes ................................................................. 5
Changes to Figures 8 and 9.............................................................. 7
Changes to Figure 12........................................................................ 8
Added Power-Up/Power-Down section...................................... 10
3/03—Data sheet changed from Rev. 0 to Rev. A
Change to Table 1 ............................................................................. 1
2/03—Revision 0: Initial Version
Rev. D | Page 2 of 12
AD5399
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
V
DD
= 5 V ± 10%, –40°C < T
A
< +105°C, unless otherwise noted.
Table 2.
Parameter
DC CHARACTERISTICS
Resolution
Differential Nonlinearity Error
Integral Nonlinearity Error
Positive Full-Scale Error
Bipolar Zero-Scale Error
Negative Full-Scale Error
ANALOG OUTPUTS
Nominal Positive Full-Scale
Positive Full-Scale Tempco
2
Nominal V
BZ
Output Voltage
Bipolar Zero Output Resistance
2
V
BZ
Output Voltage Tempco
Nominal Peak-to-Peak Output Swing
DIGITAL INPUTS
Input Logic High
Input Logic Low
Input Current
Input Capacitance
2
POWER SUPPLIES
Power Supply Range
Supply Current
Supply Current in Shutdown
Power Dissipation
3
Power Supply Sensitivity
DYNAMIC CHARACTERISTICS
2
Settling Time
Digital Feedthrough
Bipolar Zero-Scale Glitch
Capacitive Load Driving Capability
INTERFACE TIMING CHARACTERISTICS
2
, 4
SCLK Cycle Frequency
SCLK Clock Cycle Time
Input Clock Pulse Width
Data Setup Time
Data Hold Time
CS to SCLK Active Edge Setup Time
SCLK to CS Hold Time
Repeat Programming, CS High Time
Symbol
N
DNL
Codes 2048 to 2052, due to int. op amp offset
INL
V
+FSE
V
BZSE
V
–FSE
V
OUTA/B
TCV
OUTA/B
V
BZ
R
BZ
TCV
BZ
|V
+FS
| + |V
–FS
|
V
IH
V
IL
I
IL
C
IL
V
DD RANGE
I
DD
I
DD_SHDN
P
DISS
P
SS
t
S
Q
G
CL
t
CYC
t
1
t
2
, t
3
t
4
t
5
t
6
t
7
t
8
Code = 0xF
Code = 0x000
Code = 0x800
Code = 0x7FF
Code = 0x7FF, T
A
= 0°C to 70°C
Code = 0xFF, T
A
= –40°C to +105°C
Conditions
Min
12
–1
–1.2
–0.4
–0.75
–0.75
–0.75
Typ
1
Max
Unit
Bits
LSB
LSB
%FS
%FS
%FS
%FS
V
ppm/°C
ppm/°C
V
Ω
ppm/°C
ppm/°C
V
V
V
µA
pF
V
mA
µA
µA
mW
%/%
µs
nV-s
nV-s
pF
MHz
ns
ns
ns
ns
ns
ns
ns
±0.5
±0.5
±0.02
–0.15
–0.15
–0.15
4
±10
±10
2.000
1
±10
±10
4
+1
+1.2
+0.4
+0.75
+0.75
+0.75
–40
–60
1.995
–40
–60
+40
+60
2.004
+40
+60
T
A
= 0°C to 70°C
T
A
= –40°C to +105°C
Code 0x7FF to Code 0x800
V
DD
= 5 V
V
DD
= 5 V
V
IN
= 0 V or 5 V, V
DD
= 5 V
2.4
0.8
±1
5
4.5
5.5
2.6
100
500
13
+0.006
V
IH
= V
DD
or V
IL
= 0 V
V
IH
= V
DD
or V
IL
= 0 V, B14 = 0, T
A
= 0°C to 105°C
V
IH
= V
DD
or V
IL
= 0 V, B14 = 0, T
A
= –40°C to 0°C
V
IH
= V
DD
or V
IL
= 0 V, V
DD
= 5.5 V
∆V
DD
= 5 V ± 10%
0.1% error band
–0.006
1.8
10
100
9
+0.003
0.8
10
10
No oscillation
1000
33
Clock level low or high
30
15
5
0
5
0
30
1
2
Typical values represent average readings at 25°C and V
DD
= 5 V.
Guaranteed by design and not subject to production test.
3
P
DISS
is calculated from (I
DD
× V
DD
). CMOS logic level inputs result in minimum power dissipation.
4
See timing diagram (Figure 5) for location of measured values. All input control voltages are specified with t
R
= t
F
= 2 ns (10% to 90% of 3 V) and timed from a voltage
level of 1.5 V. Switching characteristics are measured using V
DD
= 5 V. Input logic should have a 1 V/µs minimum slew rate.
Rev. D | Page 3 of 12
AD5399
ABSOLUTE MAXIMUM RATINGS
T
A
= 25°C, unless otherwise noted.
Table 3.
Parameter
V
DD
to GND
V
OUTA
, V
OUTB
, V
BZ
to GND
Digital Input Voltages to GND
Operating Temperature Range
Maximum Junction Temperature (T
J MAX
)
Storage Temperature
Lead Temperature (Soldering, 10 sec)
Package Power Dissipation
Thermal Resistance, θ
JA
, MSOP-10
Rating
–0.3 V, +7.5 V
0 V, V
DD
0 V, V
DD
+ 0.3 V
–40°C to +105°C
150°C
–65°C to +150°C
300°C
(T
J MAX
– T
A
)/θ
JA
206°C/W
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. D | Page 4 of 12
AD5399
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
CLK
1
SDI
2
DGND
3
10
CS
9
AD5399
V
TP
03469-B-003
8
V
DD
TOP VIEW
(Not to Scale)
7
AGND
V
OUTB 4
V
5
6
V
BZ
OUTA
Figure 3. MSOP-10 Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
Mnemonic
CLK
SDI
DGND
V
OUTB
V
OUTA
V
BZ
AGND
V
DD
V
TP
CS
Description
Serial Clock Input. Positive edge triggered.
Serial Data Input. MSB first format.
Digital Ground.
DAC B Voltage Output (A0 = Logic 1).
DAC A Voltage Output (A0 = Logic 0).
2 V, Virtual Bipolar Zero (Active Output).
Analog Ground.
Positive Power Supply. Specified for operation at 5 V.
Connect to V
DD
. Reserved for factory testing.
Chip Select (Frame Sync Input). Allows clock and data to shift into the shift register when CS goes from high to low.
After the 16
th
clock pulse, it is not necessary to bring CS high to shift the data to the output. However, CS should be
brought high any time after the 16th clock positive edge in order to allow the next programming cycle.
Table 5. Serial Data-Word Format
ADDR
B15
A0
MSB
B14
X
B13
SD
B12
0
DATA
B11
D11
B10
D10
…
…
B3
D3
B2
D2
B1
D1
B0
D0
LSB
A0
Address Bit. Logic low selects DAC A and logic high selects DAC B.
Both channels are shut down when the SD bit is high. However, the A0 bit must be at the same state for shutdown
activation and deactivation. See the Shutdown Function section.
X
SD
0
D0–D11
Don’t Care.
Shutdown Bit. Logic high puts both DAC outputs and V
BZ
into high impedance. A0 bit must be at the same state for
shutdown activation and deactivation.
B12 must be 0.
Data Bits.
Rev. D | Page 5 of 12
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