MTD6N15
Power Field Effect Transistor
DPAK for Surface Mount
This Power FET is designed for high speed, low loss power
switching applications such as switching regulators, converters,
solenoid and relay drivers.
Features
V
(BR)DSS
150 V
N−Channel Enhancement−Mode Silicon Gate
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R
DS(on)
MAX
0.3
W
N−CHANNEL
D
I
D
MAX
6.0 A
•
•
•
•
•
•
•
Silicon Gate for Fast Switching Speeds
Low R
DS(on)
— 0.3
W
Max
Rugged — SOA is Power Dissipation Limited
Source−to−Drain Diode Characterized for Use With Inductive Loads
Low Drive Requirement — V
GS(th)
= 4.0 V Max
Surface Mount Package on 16 mm Tape
Pb−Free Package is Available
G
S
MAXIMUM RATINGS
Rating
Drain−Source Voltage
Drain−Gate Voltage (R
GS
= 1.0 MW)
Gate−Source Voltage
−
Continuous
−
Non−Repetitive (t
p
≤
50
ms)
Drain Current
−
Continuous
Drain Current
−
Pulsed
Total Power Dissipation @ T
C
= 25°C
Derate above 25°C
Total Power Dissipation @ T
A
= 25°C
Derate above 25°C (Note 1)
Total Power Dissipation @ T
A
= 25°C
(Note 1)
Derate above 25°C (Note 2)
Operating and Storage Junction
Temperature Range
Symbol
V
DSS
V
DGR
V
GS
V
GSM
I
D
I
DM
P
D
P
D
P
D
Value
150
150
±
20
±
40
6.0
20
20
0.16
1.25
0.01
1.75
0.014
T
J
, T
stg
−65
to +150
Unit
Vdc
Vdc
Vdc
Vpk
Adc
W
W/°C
W
W/°C
W
W/°C
°C
1
Gate
Y
WW
6N15
G
1 2
3
4
CASE 369C
DPAK
(Surface Mount)
STYLE 2
MARKING DIAGRAM
& PIN ASSIGNMENTS
4 Drain
YWW
T
6N15G
2
Drain
3
Source
= Year
= Work Week
= Device Code
= Pb−Free Package
THERMAL CHARACTERISTICS
Characteristic
Thermal Resistance
−
Junction−to−Case
−
Junction−to−Ambient (Note 1)
−
Junction−to−Ambient (Note 2)
Symbol
R
qJC
R
qJA
R
qJA
Value
6.25
100
71.4
Unit
°C/W
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. When surface mounted to an FR4 board using the minimum recommended
pad size.
2. When surface mounted to an FR4 board using 0.5 sq. in. drain pad size.
ORDERING INFORMATION
Device
MTD6N15T4
MTD6N15T4G
Package
DPAK
DPAK
(Pb−Free)
Shipping
†
2500/Tape & Reel
2500/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
©
Semiconductor Components Industries, LLC, 2013
May, 2013
−
Rev. 5
1
Publication Order Number:
MTD6N15/D
MTD6N15
ELECTRICAL CHARACTERISTICS
(T
J
= 25°C unless otherwise noted)
Characteristic
OFF CHARACTERISTICS
Drain−Source Breakdown Voltage (V
GS
= 0 Vdc, I
D
= 0.25 mAdc)
Zero Gate Voltage Drain Current
(V
DS
= Rated V
DSS
, V
GS
= 0 Vdc)
T
J
= 125°C
Gate−Body Leakage Current, Forward (V
GSF
= 20 Vdc, V
DS
= 0)
Gate−Body Leakage Current, Reverse (V
GSR
= 20 Vdc, V
DS
= 0)
ON CHARACTERISTICS
(Note 3)
Gate Threshold Voltage (V
DS
= V
GS
, I
D
= 1.0 mAdc)
T
J
= 100°C
Static Drain−Source On−Resistance (V
GS
= 10 Vdc, I
D
= 3.0 Adc)
Drain−Source On−Voltage (V
GS
= 10 Vdc)
(I
D
= 6.0 Adc)
(I
D
= 3.0 Adc, T
J
= 100°C)
Forward Transconductance (V
DS
= 15 Vdc, I
D
= 3.0 Adc)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS*
(T
J
= 100°C)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Total Gate Charge
Gate−Source Charge
Gate−Drain Charge
SOURCE−DRAIN DIODE CHARACTERISTICS*
Forward On−Voltage
Forward Turn−On Time
Reverse Recovery Time
3. Pulse Test: Pulse Width
≤
300
ms,
Duty Cycle
≤
2%.
(I
S
= 6.0 Adc, di/dt = 25 A/ms, V
GS
= 0 Vdc)
V
SD
t
on
t
rr
1.3 (Typ)
325 (Typ)
2.0
−
Vdc
ns
Limited by stray inductance
(V
DS
= 0.8 Rated V
DSS
,
I
D
= Rated I
D
, V
GS
= 10 Vdc)
(See Figure 12)
(V
DD
= 25 Vdc, I
D
= 3.0 Adc, R
G
= 50
W)
(See Figures 13 and 14)
t
d(on)
t
r
t
d(off)
t
f
Q
g
Q
gs
Q
gd
−
−
−
−
15 (Typ)
8.0 (Typ)
7.0 (Typ)
50
180
200
100
30
−
−
nC
ns
(V
DS
= 25 Vdc, V
GS
= 0 Vdc, f = 1.0 MHz)
(See Figure 11)
C
iss
C
oss
C
rss
−
−
−
1200
500
120
pF
V
GS(th)
R
DS(on)
V
DS(on)
2.0
1.5
−
−
−
2.5
4.5
4.0
0.3
1.8
1.5
−
Vdc
W
Vdc
V
(BR)DSS
I
DSS
150
−
−
−
−
−
10
100
100
100
Vdc
mAdc
Symbol
Min
Max
Unit
I
GSSF
I
GSSR
nAdc
nAdc
g
FS
mhos
2.5
PD, POWER DISSIPATION (WATTS)
25
2
20
T
C
1.5
15
1
10
0.5
5
0
T
A
0
T
C
25
50
75
100
125
150
Figure 1. Power Derating
T, TEMPERATURE (°C)
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2
MTD6N15
TYPICAL ELECTRICAL CHARACTERISTICS
VGS(th) , GATE THRESHOLD VOLTAGE (VOLTS)
24
10 V
I D , DRAIN CURRENT (AMPS)
20
16
8V
12
8
4
0
7V
6V
5V
0
10
20
30
40
50
V
DS
, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
60
9V
T
J
= 25°C
3.6
V
DS
= V
GS
I
D
= 1 mA
3.2
2.8
2.4
2
- 50
0
50
100
T
J
, JUNCTION TEMPERATURE (°C)
150
Figure 2. On−Region Characteristics
V(BR)DSS , DRAIN-TO-SOURCE BREAKDOWN VOLTAGE
(NORMALIZED)
Figure 3. Gate−Threshold Voltage Variation
With Temperature
14
V
DS
= 10 V
I D , DRAIN CURRENT (AMPS)
12
10
8
6
4
2
0
100°C
- 55°C
T
J
= 25°C
2
V
GS
= 0 V
I
D
= 0.25 mA
1.6
1.2
0.8
0.4
4
6
8
V
GS
, GATE-TO-SOURCE VOLTAGE (VOLTS)
10
0
- 50
0
50
100
150
T
J
, JUNCTION TEMPERATURE (°C)
200
Figure 4. Transfer Characteristics
Figure 5. Breakdown Voltage Variation
With Temperature
R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)
V
GS
= 10 V
0.25
0.20
0.15
0.10
0.05
0
RDS(on) , DRAIN-TO-SOURCE RESISTANCE
(NORMALIZED)
0.30
T
J
= 100°C
2
V
GS
= 10 V
I
D
= 3 A
1.6
25°C
1.2
- 55°C
0.8
0.4
0
4
8
12
16
I
D
, DRAIN CURRENT (AMPS)
20
0
- 50
0
50
100
150
T
J
, JUNCTION TEMPERATURE (°C)
200
Figure 6. On−Resistance versus Drain Current
Figure 7. On−Resistance Variation
With Temperature
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3
MTD6N15
SAFE OPERATING AREA
20
I D , DRAIN CURRENT (AMPS)
10
5
2
1
0.5
0.2
0.1
R
DS(on)
LIMIT
THERMAL LIMIT
PACKAGE LIMIT
T
C
= 25°C
V
GS
= 20 V SINGLE PULSE
10 ms
20
100
ms
1 ms
10
ms
I D , DRAIN CURRENT (AMPS)
15
10
T
J
≤
150°C
dc
5
0.05
0.03
0.3 0.5 0.7 1
2 3 5 7 10
20 30 50 70 100
V
DS
, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
200 300
0
0
20
40
60
80
100
120
140
V
DS
, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
160
Figure 8. Maximum Rated Forward Biased
Safe Operating Area
Figure 9. Maximum Rated Switching
Safe Operating Area
SWITCHING SAFE OPERATING AREA
FORWARD BIASED SAFE OPERATING AREA
The FBSOA curves define the maximum drain−to−source
voltage and drain current that a device can safely handle
when it is forward biased, or when it is on, or being turned
on. Because these curves include the limitations of
simultaneous high voltage and high current, up to the rating
of the device, they are especially useful to designers of linear
systems. The curves are based on a case temperature of 25°C
and a maximum junction temperature of 150°C. Limitations
for repetitive pulses at various case temperatures can be
determined by using the thermal response curves. Motorola
Application Note, AN569, “Transient Thermal
Resistance−General Data and Its Use” provides detailed
instructions.
The switching safe operating area (SOA) of Figure 9 is the
boundary that the load line may traverse without incurring
damage to the MOSFET. The fundamental limits are the
peak current, I
DM
and the breakdown voltage, V
(BR)DSS
.
The switching SOA shown in Figure 8 is applicable for both
turn−on and turn−off of the devices for switching times less
than one microsecond.
The power averaged over a complete switching cycle
must be less than:
T
J(max)
−
T
C
R
qJC
r(t), EFFECTIVE TRANSIENT
THERMAL RESISTANCE (NORMALIZED)
0.7
0.5
0.3
0.2
D = 0.5
0.2
0.1
0.1 0.05
0.07
0.02
0.05
0.03
0.02
0.01
0.01
0.01
SINGLE PULSE
P
(pk)
t
1
t
2
DUTY CYCLE, D = t
1
/t
2
0.1
0.2 0.3
0.5
1
2 3
5
10
t, TIME OR PULSE WIDTH (ms)
20
R
qJC
(t) = r(t) R
qJC
R
qJC
(t) = 6.25°C/W MAX
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
1
T
J(pk)
- T
C
= P
(pk)
R
qJC
(t)
50
100
200
500
1000
0.02 0.03
0.05
Figure 10. Thermal Response
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4
MTD6N15
2000
VGS, GATE SOURCE VOLTAGE (VOLTS)
1600
C, CAPACITANCE (pF)
T
J
= 25°C
V
GS
= 0
16
T
J
= 25°C
I
D
= 6 A
12
75 V
8
V
DS
= 50 V
120 V
1200
800
V
DS
= 0
C
iss
C
oss
C
rss
25
30
400
4
0
15
10
5
V
GS
0
5
V
DS
10
15
20
35
0
0
4
8
12
Q
g
, TOTAL GATE CHARGE (nC)
16
20
GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 11. Capacitance Variation
Figure 12. Gate Charge versus
Gate−To−Source Voltage
RESISTIVE SWITCHING
V
DD
t
on
R
L
V
out
V
in
PULSE GENERATOR
R
gen
50
W
z = 50
W
50
W
INPUT, V
in
50%
10%
PULSE WIDTH
DUT
t
d(on)
OUTPUT, V
out
INVERTED
10%
90%
50%
t
r
90%
t
d(off)
t
off
t
f
90%
Figure 13. Switching Test Circuit
Figure 14. Switching Waveforms
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5
51mcu
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