TECHNICAL DATA
KK74HC164А
8-Bit Serial-Input/Parallel-Output
Shift Register
High-Performance Silicon-Gate CMOS
The
KK74HC164A
is identical in pinout to the LS/ALS164. The
device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
The
KK74HC164A
is an 8-bit, serial-input to parallel-output shift
register. Two serial data inputs, A1 and A2, are provided so that one input
may be used as a data enable. Data is entered on each rising edge of the
clock. The active-low asynchronous Reset overrides theClock and Serial
Data inputs.
•
Outputs Directly Interface to CMOS, NMOS, and TTL
•
Operating Voltage Range: 2.0 to 6.0 V
•
Low Input Current: 1.0
µA
•
High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
KK74HC164АN
Plastic
KK74HC164АD
SOIC
T
A
= -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Inputs
RESET
L
H
PIN 14 =V
CC
PIN 7 = GND
H
H
CLOCK
X
A1 A2
X X
X X
H D
D H
L
Outputs
QA QB…QH
L… L
no change
D
QAn…QGn
D
QAn…QGn
D = data input
X = don’t care
Q
An
- Q
Gn
= data shifted from the previous stage on a
rising edge at the clock input.
1
KK74HC164А
MAXIMUM RATINGS
*
Symbol
V
CC
V
IN
V
OUT
I
IN
I
OUT
I
CC
P
D
Tstg
T
L
*
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, V
CC
and GND Pins
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
Value
-0.5 to +7.0
-1.5 to V
CC
+1.5
-0.5 to V
CC
+0.5
±20
±25
±50
750
500
-65 to +150
260
Unit
V
V
V
mA
mA
mA
mW
°C
°C
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
IN
, V
OUT
T
A
t
r
, t
f
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time
(Figure 1)
V
CC
=2.0 V
V
CC
=4.5 V
V
CC
=6.0 V
Min
2.0
0
-55
0
0
0
Max
6.0
V
CC
+125
1000
500
400
Unit
V
V
°C
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this
high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range GND≤(V
IN
or
V
OUT
)≤V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
CC
). Unused
outputs must be left open.
2
KK74HC164А
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
V
CC
Symbol
Parameter
Test Conditions
V
Guaranteed Limit
25
°C
to
-55°C
1.5
3.15
4.2
0.3
0.9
1.2
1.9
4.4
5.9
3.98
5.48
0.1
0.1
0.1
0.26
0.26
±0.1
8.0
≤85
°C
1.5
3.15
4.2
0.3
0.9
1.2
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
±1.0
80
≤125
°C
1.5
3.15
4.2
0.3
0.9
1.2
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
±1.0
160
µA
µA
V
Unit
V
IH
Minimum High-
Level Input Voltage
Maximum Low -
Level Input Voltage
Minimum High-
Level Output Voltage
V
OUT
=0.1 V or V
CC
-0.1 V
⎢I
OUT
⎢≤
20
µA
V
OUT
=0.1 V or V
CC
-0.1 V
⎢I
OUT
⎢ ≤
20
µA
V
IN
= V
IH
or V
IL
⎢I
OUT
⎢ ≤
20
µA
V
IN
= V
IH
or V
IL
⎢I
OUT
⎢ ≤
4.0 mA
⎢I
OUT
⎢ ≤
5.2 mA
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
6.0
V
V
IL
V
V
OH
V
V
OL
Maximum Low-
Level Output Voltage
V
IN
=V
IH
or V
IL
⎢I
OUT
⎢ ≤
20
µA
V
IN
=V
IH
or V
IL
⎢I
OUT
⎢ ≤
4.0 mA
⎢I
OUT
⎢ ≤
5.2 mA
I
IN
I
CC
Maximum Input
Leakage Current
Maximum Quiescent
Supply Current
(per Package)
V
IN
=V
CC
or GND
V
IN
=V
CC
or GND
I
OUT
=0µA
3
KK74HC164А
AC ELECTRICAL CHARACTERISTICS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Symbol
Parameter
V
Guaranteed Limit
25
°C
to
-55°C
6.0
30
35
175
35
30
205
41
35
75
15
13
10
50
10
9
5
5
5
5
5
5
80
16
14
80
16
14
1000
500
400
≤85°C
≤125°C
Unit
f
max
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
Maximum Propagation Delay,Clock to Q (Figures
1 and 4)
Maximum Propagation Delay,Reset to Q
(Figures 2 and 4)
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
Maximum Input Capacitance
Minimum Setup Time,A1 or A2 to Clock
(Figure 3)
Minimum Hold Time, Clock to A1 or A2
(Figure 3)
Minimum Recovery Time, Reset Inactive to
Clock (Figure 2)
Minimum Pulse Width, Reset (Figure 2)
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
-
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.8
24
28
220
44
37
255
51
43
95
19
16
10
65
13
11
5
5
5
5
5
5
100
20
17
100
20
17
1000
500
400
4.0
20
24
265
53
45
310
62
53
110
22
19
10
75
15
13
5
5
5
5
5
5
120
24
20
120
24
20
1000
500
400
MHz
t
PLH
, t
PHL
ns
t
PHL
ns
t
TLH
, t
THL
ns
C
IN
t
SU
pF
ns
t
h
ns
t
rec
ns
t
w
ns
t
w
Minimum Pulse Width, Clock (Figure 1)
ns
t
r,
t
f
Maximum Input Rise and Fall Times (Figure 1)
ns
Power Dissipation Capacitance (Per Package)
C
PD
Used to determine the no-load dynamic power
consumption:
P
D
=C
PD
V
CC2
f+I
CC
V
CC
Typical @25°C,V
CC
=5.0 V
140
pF
4
KK74HC164А
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
Figure 3. Switching Waveforms
Figure 4. Test Circuit
TIMING DIAGRAM
EXPANDED LOGIC DIAGRAM
5
Talking
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