TECHNICAL DATA
KK74HC166A
8-Bit Serial or Parallel-Input/
Serial-Output Shift Register
High-Performance Silicon-Gate CMOS
The KK74HC166A is identical in pinout to the LS/ALS166. The
device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
This device is a parallel-in or serial-in, serial-out shift register with
gated clock inputs and an overriding clear input. The shift/load input
establishes the parallel-in or serial-in mode. When high, this input enables
the serial data input and couples the eight flip-flops for serial shifting
with each clock pulse. Synchronous loading occurs on the next clock
pulse when this is low and the parallel data inputs are enabled. Serial data
flow is inhibited during parallel loading. Clocking is done on the low-to-
high level edge of the clock pulse via a two input positive NOR gate,
which permits one input to be used as a clock enable or clock inhibit
function. Clocking is inhibited when either of the clock inputs are held
high, holding either input low enables the other clock input. This will
allow the system clock to be free running and the register stopped on
command with the other clock input. A change from low-to-high on the
clock inhibit input should only be done when the clock input is high. A
buffered direct clear input overrides all other inputs, including the clock,
andsets all flip-flop to zero.
•
Outputs Directly Interface to CMOS, NMOS, and TTL
•
Operating Voltage Range: 2.0 to 6.0 V
•
Low Input Current: 1.0
µA
•
High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
KK74HC166AN Plastic
KK74HC166AD SOIC
T
A
= -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 16 =V
CC
PIN 8 = GND
1
KK74HC166A
MAXIMUM RATINGS
*
Symbol
V
CC
V
IN
V
OUT
I
IN
I
OUT
I
CC
P
D
Tstg
T
L
*
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, V
CC
and GND Pins
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
Value
-0.5 to +7.0
-1.5 to V
CC
+1.5
-0.5 to V
CC
+0.5
±20
±25
±50
750
500
-65 to +150
260
Unit
V
V
V
mA
mA
mA
mW
°C
°C
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
IN
, V
OUT
T
A
t
r
, t
f
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 1)
V
CC
=2.0 V
V
CC
=4.5 V
V
CC
=6.0 V
Min
2.0
0
-55
0
0
0
Max
6.0
V
CC
+125
1000
500
400
Unit
V
V
°C
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this
high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range GND≤(V
IN
or
V
OUT
)≤V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
CC
). Unused
outputs must be left open.
2
KK74HC166A
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
V
CC
Symbol
Parameter
Test Conditions
V
Guaranteed Limit
25
°C
to
-55°C
1.5
3.15
4.2
0.3
0.9
1.2
1.9
4.4
5.9
3.98
5.48
0.1
0.1
0.1
0.26
0.26
±0.1
8.0
≤85
°C
1.5
3.15
4.2
0.3
0.9
1.2
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
±1.0
80
≤125
°C
1.5
3.15
4.2
0.3
0.9
1.2
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
±1.0
160
µA
µA
V
Unit
V
IH
Minimum High-
Level Input Voltage
Maximum Low -
Level Input Voltage
Minimum High-
Level Output Voltage
V
OUT
=0.1 V or V
CC
-0.1 V
⎢I
OUT
⎢≤
20
µA
V
OUT
=0.1 V or V
CC
-0.1 V
⎢I
OUT
⎢ ≤
20
µA
V
IN
=V
IH
or V
IL
⎢I
OUT
⎢ ≤
20
µA
V
IN
=V
IH
or V
IL
⎢I
OUT
⎢ ≤
4.0 mA
⎢I
OUT
⎢ ≤
5.2 mA
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
6.0
V
V
IL
V
V
OH
V
V
OL
Maximum Low-
Level Output Voltage
V
IN
=V
IH
or V
IL
⎢I
OUT
⎢ ≤
20
µA
V
IN
=V
IH
or V
IL
⎢I
OUT
⎢ ≤
4.0 mA
⎢I
OUT
⎢ ≤
5.2 mA
I
IN
I
CC
Maximum Input
Leakage Current
Maximum Quiescent
Supply Current
(per Package)
V =V
CC
or GND
V
IN
=V
CC
or GND
I
OUT
=0µA
FUNCTION TABLE
Inputs
Clear
L
H
H
H
H
H
Shift/Load
X
X
L
H
H
X
Clock
Inhibit
X
X
L
L
L
H
X
Clock
X
S
A
X
X
X
H
L
X
Parallel
A...H
X
X
a...h
X
X
X
a
H
L
Internal
Outputs
Q
A
L
Q
B
L
No change
b
Q
An
Q
An
No change
h
Q
Gn
Q
Gn
Output
Q
H
L
X = don’t care
a...h = the level of steady state input voltage at input A trough H respectively
3
KK74HC166A
AC ELECTRICAL CHARACTERISTICS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Symbol
Parameter
V
Guaranteed Limit
25
°C
to
-55°C
6.0
31
36
140
28
24
150
30
26
75
16
14
10
≤85°C
≤125°C
Unit
f
max
Minimum Clock Frequency (50% Duty Cycle)
(Figures 2 and 4)
Maximum Propagation Delay, Clock (or Clock
Inhibit) to Q
H
(Figures 2,3 and 4)
Maximum Propagation Delay , Clear to Q
H
(Figures 1 and 4)
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
Maximum Input Capacitance
Power Dissipation Capacitance (Per Package)
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
-
5.0
25
28
175
35
30
200
40
34
95
20
18
10
4.2
21
25
210
42
36
230
48
40
110
25
20
10
MHz
t
PLH
, t
PHL
ns
t
PHL
ns
t
TLH
, t
THL
ns
C
IN
pF
Typical @25°C,V
CC
=5.0 V
140
pF
C
PD
Used to determine the no-load dynamic power
consumption:
P
D
=C
PD
V
CC2
f+I
CC
V
CC
TIMING REQUIREMENTS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Symbol
t
su
Parameter
Minimum Setup Time, Shift/Load to
Clock (Figure 3)
Minimum Setup Time, Data before
Clock (or Clock Inhibit) (Figure 3)
Minimum Pulse Width, Clock (or
Clock Inhibit) (Figure 2)
V
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Guaranteed Limit
25
°C
to
-55°C
80
16
14
80
16
14
80
16
14
≤85°C
100
20
18
100
20
18
100
20
17
≤125°C
120
24
20
120
24
20
120
24
20
Unit
ns
t
su
ns
t
w
ns
4
KK74HC166A
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
Figure 3. Switching Waveforms
Figure 4. Test Circuit
5
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