KK74HC4046A datasheet, PDF - EEWORLD Datasheet

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KK74HC4046A: DescriptionPhase-Locked Loop High-Performance Silicon-Gate CMOS; File Size287KB，12 Pages; ManufacturerKODENSHI; Websitehttp://www.kodenshi.co.jp

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KK74HC4046A Overview

Phase-Locked Loop High-Performance Silicon-Gate CMOS

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TECHNICAL DATA

Phase-Locked Loop

High-Performance Silicon-Gate CMOS

KK74HC4046A

The device inputs are compatible with standard CMOS outputs; with

pullup resistors, they are compatible with LS/ALSTTL outputs.

The KK74HC4046A phase-locked loop contains three phase

comparators, a voltage-controlled oscillator (VCO) and unity gain op-

amp DEM

OUT

. The comparators have two common signal inputs,

COMP

, and SIG

. Input SIG

and COMP

can be used directly

coupled to large voltage signals, or indirectly coupled (with a series

capacitor to small voltage signals). The self-bias circuit adjusts small

voltage signals in the linear region of the amplifier. Phase comparator 1

(an exclusive OR gate) provides a digital error signal PC1

OUT

and

maintains 90 degrees phase shift at the center frequency between SIG

and COMP

signals (both at 50% duty cycle). Phase comparator 2 (with

ORDERING INFORMATION

leading-edge sensing logic) provides digital error signals PC2

OUT

and

KK74HC4046AN Plastic

PCP

OUT

and maintains a 0 degree phase shift between SIG

and COMP

KK74HC4046AD SOIC

signals (duty cycle is immaterial). The linear VCO produces an output

= -55° to 125° C for all packages

signal VCO

OUT

whose frequency is determined by the voltage of input

VCO

signal and the capacitor and resistors connected to pins C1A,

C1B, R1 and R2. The unity gain op-amp output DEM

OUT

with an external

resistor is used where the VCO

signal is needed but no loading can be tolerated. The inhibit input, when high,

disables the VCO and all on-amps to minimize standby power consumption.

Applications include FM and FSK modulation and demodulation, frequency synthesis and multiplication,

frequency discrimination, tone decoding, data synchronization and conditioning, voltage-to-frequency conversion and

motor speed control.

•

Low Power Consumption Characteristic of CMOS Device

PIN ASSIGNMENT

•

Operating Speeds Similary to LS/ALSTTL

•

Wide Operating Voltage Range: 3.0 to 6.0 V

•

Low Input Current: 1.0

µA

Maximum (except SIG

and COMP

)

•

Low Quiescent Current: 80

µA

Maximum (VCO disabled)

•

High Noise Immunity Characteristic of CMOS Devices

•

Diode Protection on all Inputs

Pin No.

Symbol

PCP

OUT

PC1

OUT

COMP

VCO

OUT

INH

C1A

C1B

GND

VCO

DEM

OUT

PC2

OUT

SIG

PC3

OUT

Name and Function

Phase Comparator Pulse Output

Phase Comparator 1 Output

Comparator Input

VCO Output

Inhibit Input

Capacitor C1 Connection A

Capacitor C1 Connection B

Ground (0 V) V

VCO Input

Demodulator Output

Resistor R1 Connection

Resistor R2 Connection

Phase Comparator 2 Output

Signal Input

Phase Comparator 3 Output

Positive Supply Voltage

KK74HC4046A Related Products

	KK74HC4046A	KK74HC4046AD	KK74HC4046AN
Description	Phase-Locked Loop High-Performance Silicon-Gate CMOS	Phase-Locked Loop High-Performance Silicon-Gate CMOS	Phase-Locked Loop High-Performance Silicon-Gate CMOS
Maker	-	KODENSHI	KODENSHI
package instruction	-	SOP, SOP16,.25	DIP, DIP16,.3
Reach Compliance Code	-	unknow	unknow
JESD-30 code	-	R-PDSO-G16	R-PDIP-T16
Number of terminals	-	16	16
Maximum operating temperature	-	125 °C	125 °C
Minimum operating temperature	-	-55 °C	-55 °C
Package body material	-	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	-	SOP	DIP
Encapsulate equivalent code	-	SOP16,.25	DIP16,.3
Package shape	-	RECTANGULAR	RECTANGULAR
Package form	-	SMALL OUTLINE	IN-LINE
power supply	-	2/6 V	2/6 V
Certification status	-	Not Qualified	Not Qualified
surface mount	-	YES	NO
technology	-	CMOS	CMOS
Temperature level	-	MILITARY	MILITARY
Terminal form	-	GULL WING	THROUGH-HOLE
Terminal pitch	-	1.27 mm	2.54 mm
Terminal location	-	DUAL	DUAL

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