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KK74LV02D

Description
Quad 2-Input NOR Gate
Categorylogic    logic   
File Size178KB,5 Pages
ManufacturerKODENSHI
Websitehttp://www.kodenshi.co.jp
Download Datasheet Parametric Compare View All

KK74LV02D Overview

Quad 2-Input NOR Gate

KK74LV02D Parametric

Parameter NameAttribute value
package instructionSOP, SOP14,.25
Reach Compliance Codeunknow
JESD-30 codeR-PDSO-G14
Load capacitance (CL)50 pF
Logic integrated circuit typeNOR GATE
MaximumI(ol)0.006 A
Number of terminals14
Maximum operating temperature125 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Encapsulate equivalent codeSOP14,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE
power supply3.3 V
Prop。Delay @ Nom-Su15 ns
Certification statusNot Qualified
Schmitt triggerNO
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelAUTOMOTIVE
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Base Number Matches1
TECHNICAL DATA
KK74LV02
Quad 2-Input NOR Gate
The
KK74LV02
is a low-voltage Si-gate CMOS device that is pin
and function compatible with 74HC/HCT02A, 74ALS02
Features:
Wide Operating Voltage: 1.0~5.5 V
Input voltage levels are compatible with standard C-
MOS levels
Accepts TTL input levels between V
CC
=2.7 V and
V
CC
=3.6 V
Output voltage levels are compatible with input levels
C-MOS, N-MOS and TTL microcircuits.
Maximum input current : 1.0 mA
ORDERING INFORMATION
KK74LV02N
DIP
KK74LV02D
SOIC
Consumption current : 8 mA.
T
A
= -40° to 125° C for all
packages
KK74LV02
truth table
3
Input
A
L
L
H
H
B
L
H
L
H
Output
Y=
A
+
B
H
L
L
L
Note – H - high voltage level;
L - low voltage level;
Pinout
Y1
01
Pins description in
KK74LV02
Pin No.
01
14
Symbol
Pin description
Output
Input
Input
Output
Input
Input
Common output
Input
Input
Output
Input
Input
Output
Supply output from voltage
source
Vcc
Y4
B4
A4
Y3
B3
A3
Y1
А1
В1
A1
02
B1
03
13
12
11
10
09
08
02
03
04
05
06
07
08
09
10
11
12
13
14
Y2
А2
В2
GND
А3
В3
Y2
04
A2
05
Y3
А4
В4
B2
06
GND
07
Y4
V
CC
1

KK74LV02D Related Products

KK74LV02D KK74LV02 KK74LV02N
Description Quad 2-Input NOR Gate Quad 2-Input NOR Gate Quad 2-Input NOR Gate
package instruction SOP, SOP14,.25 - DIP, DIP14,.3
Reach Compliance Code unknow - unknow
JESD-30 code R-PDSO-G14 - R-PDIP-T14
Load capacitance (CL) 50 pF - 50 pF
Logic integrated circuit type NOR GATE - NOR GATE
MaximumI(ol) 0.006 A - 0.006 A
Number of terminals 14 - 14
Maximum operating temperature 125 °C - 125 °C
Minimum operating temperature -40 °C - -40 °C
Package body material PLASTIC/EPOXY - PLASTIC/EPOXY
encapsulated code SOP - DIP
Encapsulate equivalent code SOP14,.25 - DIP14,.3
Package shape RECTANGULAR - RECTANGULAR
Package form SMALL OUTLINE - IN-LINE
power supply 3.3 V - 3.3 V
Prop。Delay @ Nom-Su 15 ns - 15 ns
Certification status Not Qualified - Not Qualified
Schmitt trigger NO - NO
Nominal supply voltage (Vsup) 3.3 V - 3.3 V
surface mount YES - NO
technology CMOS - CMOS
Temperature level AUTOMOTIVE - AUTOMOTIVE
Terminal form GULL WING - THROUGH-HOLE
Terminal pitch 1.27 mm - 2.54 mm
Terminal location DUAL - DUAL
Base Number Matches 1 - 1

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