TECHNICAL DATA
KK74LV174
Hex D-type flip-flop with reset; positive edge-trigger
The 74LV174 is a low–voltage Si–gate CMOS device and is pin and
function compatible with the 74HC/HCT174.
The 74LV174 has six edge–triggered D–type flip–flops with individual D
inputs and Q outputs. The common clock (CP) and master reset (MR)
inputs load and reset (clear) all flip–flops simultaneously.
The register is fully edge–triggered. The state of each D input, one set–up
time prior to the LOW–to–HIGH clock transition, is transferred to the
corresponding output of the flip–flop.
A LOW level on the MR input forces all outputs LOW, independently of
clock or data inputs.
The device is useful for applications requiring true outputs only and clock
and master reset inputs that are common to all storage elements.
•
Output voltage levels are compatible with input levels of CMOS,
NMOS and TTL IC
S
•
Supply voltage range: 1.2 to 5.5 V
•
Low input current: 1.0
µА;
0.1
µА
at
Т
= 25
°С
•
Output current: 6 mA at Vcc = 3.0 V; 12 mA at Vcc = 4.5 V
•
High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
KK74LV174N
Plastic
KK74LV174D
SOIC
T
A
= -40° to 125° C for all packages
PIN ASSIGNMENT
MR
Q0
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V CC
Q5
D5
D4
Q4
D3
Q3
CP
LOGIC DIAGRAM
D0
D1
Q1
D2
Q2
GND
FUNCTION TABLE
CP
Inputs
MR
CP
X
Dn
X
H
L
L
X
X
Outputs
Qn
L
H
L
no change
no change
MR
L
H
PIN 16=V
CC
PIN 08 = GND
H
H
H
H= high level
L = low level
X = don’t care
1
KK74LV174
MAXIMUM RATINGS
*
Symbol
V
CC
I
IK
*
1
I
OK
*
2
I
O
*
3
I
CC
I
GND
P
D
DC supply voltage
Input diode current
Output diode current
Output source or sink current
V
CC
current
GND current
Power dissipation per package: *
4
Plastic DIP
SO
Storage Temperature
Lead Temperature, 1.5 mm (Plastic DIP Package), 0.3 mm
(SO Package) from Case for 4 Seconds
Parameter
Value
-0.5 to +5.0
±20
±50
±25
±50
±50
750
500
-65 to +150
260
°C
°C
Unit
V
mA
mA
mA
mA
mA
mW
Tstg
T
L
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
*
1
V
I
< -0.5 V or V
I
> V
CC
+ 0.5 V
*
2
V
O
< -0.5 V or V
O
> V
CC
+ 0.5 V
*
3
-0.5 V < V
O
< V
CC
+ 0.5 V
*
4
Derating - Plastic DIP: - 12 mW/°C from 70° to 125°C
SO Package: : - 8 mW/°C from 70° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
IN
V
OUT
T
A
t
r
, t
f
DC Supply Voltage
DC Input Voltage
DC Output Voltage
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 1)
1.0
В
≤V
CC
<2.0
В
2.0
В
≤V
CC
<2.7
В
2.7
В
≤V
CC
<3.6
В
3.6
В
≤V
CC
≤5.5
В
Parameter
Min
1.2
0
0
-40
0
0
0
0
Max
5.5
V
CC
V
CC
+125
500
200
100
50
Unit
V
V
V
°C
ns/V
This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this
high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range GND≤(V
IN
or
V
OUT
)≤V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
CC
). Unused
outputs must be left open.
2
KK74LV174
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Test
Symbol
V
IH
Parameter
HIGH level input
voltage
conditions
V
CC
V
1.2
2.0
2.7
3.0
3.6
4.5
5.5
1.2
2.0
2.7
3.0
3.6
4.5
5.5
V
I
= V
IH
or V
IL
I
O
= -100
µА
1.2
2.0
2.7
3.0
3.6
4.5
5.5
3.0
4.5
1.2
2.0
2.7
3.0
3.6
4.5
5.5
3.0
4.5
5.5
5.5
2.7
3.6
-40°C to 25°C
min
0.9
1.4
2.0
2.0
2.0
3.15
3.85
-
-
-
-
-
-
-
1.05
1.85
2.55
2.85
3.45
4.35
5.35
2.48
3.70
-
-
-
-
-
-
-
-
-
-
-
-
max
-
-
-
-
-
-
-
0.3
0.6
0.8
0.8
0.8
1.35
1.65
-
-
-
-
-
-
-
-
-
0.15
0.15
0.15
0.15
0.15
0.15
0.15
0.33
0.40
±0.1
8.0
0.2
0.2
Guaranteed Limit
85°C
min
0.9
1.4
2.0
2.0
2.0
3.15
3.85
-
-
-
-
-
-
-
1.0
1.8
2.5
2.8
3.4
4.3
5.3
2.34
3.60
-
-
-
-
-
-
-
-
-
-
-
-
max
-
-
-
-
-
-
-
0.3
0.6
0.8
0.8
0.8
1.35
1.65
-
-
-
-
-
-
-
-
-
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.40
0.55
±1.0
80
0.5
0.5
125°C
min
0.9
1.4
2.0
2.0
2.0
3.15
3.85
-
-
-
-
-
-
-
1.0
1.8
2.5
2.8
3.4
4.3
5.3
2.20
3.50
-
-
-
-
-
-
-
-
-
-
-
-
max
-
-
-
-
-
-
-
0.3
0.6
0.8
0.8
0.8
1.35
1.65
-
-
-
-
-
-
-
-
-
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.50
0.65
±1.0
160
0.85
0.85
V
Unit
V
IL
LOW level input
voltage
V
V
OH
HIGH level output
voltage
V
V
I
= V
IH
or V
IL
I
O
= -6 mА
V
I
= V
IH
or V
IL
I
O
= -12 mА
V
OL
LOW level output
voltage
V
I
= V
IH
or V
IL
I
O
= 100
µА
V
V
V
V
I
= V
IH
or V
IL
I
O
= 6 mА
V
I
= V
IH
or V
IL
I
O
= 12 mА
I
I
I
CC
I
CC1
Input current
Supply current
Additional
quiescent supply
current per input
V
I
= V
CC
or 0 V
V
I
=V
CC
or 0 V
I
O
= 0
µА
V
I
=V
CC
–
0.6 V
V
V
µА
µА
mA
3
KK74LV174
AC ELECTRICAL CHARACTERISTICS
(C
L
=50 pF, R
L
= 1 kΩ, t
r
=t
f
=2.5 ns)
Test
Symbol
Parameter
conditions
V
I
= 0 V or V
CC
Figure 1, 4
V
CC
V
1.2
2.0
2.7
3.0
4.5
1.2
2.0
2.7
3.0
4.5
1.2
2.0
2.7
3.0
4.5
1.2
2.0
2.7
3.0
4.5
1.2
2.0
2.7
3.0
4.5
1.2
2.0
2.7
3.0
4.5
1.2
2.0
2.7
3.0
4.5
5.0
5.5
1.2
2.0
2.7
3.0
4.5
min
t
PHL,
t
PLH
Propagation delay CP to
Qn
-
-
-
-
-
-
-
-
-
-
100
28
21
17
14
100
28
21
17
14
40
19
13
11
9
50
5
5
5
5
50
5
5
5
5
-
-
-
-
-
-
-
Guaranteed Limit
-40°C to 25°C
max
200
34
24
20
17
160
34
24
20
17
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
7.0
34
2.0
16
22
27
32
-
-
-
-
-
-
-
-
-
-
140
34
25
20
17
140
34
25
20
17
60
22
16
13
11
50
5
5
5
5
50
5
5
5
5
-
-
-
-
-
-
-
85°C
min
max
230
43
31
25
21
190
43
31
25
21
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.0
14
19
24
27
-
-
-
-
-
-
-
-
-
-
180
41
30
24
20
180
41
30
24
20
80
26
19
15
13
50
5
5
5
5
50
5
5
5
5
-
-
-
-
-
-
-
125°C
min
max
260
53
39
31
26
220
53
39
31
26
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.0
12
16
20
24
ns
Unit
t
PHL
Propagation delay MR to
Qn
V
I
= 0 V or V
CC
Figure 2, 4
ns
t
W
Clock pulse width HIGH
or LOW
V
I
= 0 V or V
CC
Figure 1, 4
ns
t
W
Master reset pulse width
LOW
V
I
= 0 V or V
CC
Figure 1, 4
ns
t
REM
Removal time MR to CP
V
I
= 0 V or V
CC
Figure 3, 4
ns
t
SU
Set-up time Dn to CP
V
I
= 0
В
or V
CC
Рису½ок
3, 4
ns
t
h
Hold time Dn to CP
V
I
= 0
В
or V
CC
Рису½ок
2, 4
ns
C
I
C
PD
fmax
Input capacitance
Т
A
= 25°C
pF
pF
MHz
Power dissipation
V
I
= 0 V or V
CC
capacitance (per flip-flop) T = 25°C
A
Maximum clock pulse
frequency
V
I
= 0
В
or V
CC
Рису½ок
1
4
KK74LV174
t
w
tr
CP
10%
V
M
(1)
tf
90%
V
1
(2)
MR
t
PHL
Q
V
M
(1)
V
1
(2)
GND
t
w
t
PLH
1/fmax
GND
V
OH
V
OL
V
M
(1)
t
PHL
V
OH
V
OL
Q
V
M
(1)
t
rec
CP
V
M
(1)
V
1
(2)
GND
Figure 1. Switching Waveforms
VALID
Figure 2. Switching Waveforms
TEST POINT
DATA
V
M
(1)
V
1
(2)
GND
t
su
t
h
V
M
(1)
DEVICE
UNDER
TEST
OUTPUT
R
L
C
L
*
CP
V
1
(2)
GND
* Includes all probe and jig capacitance
Figure 3. Switching Waveforms
Note:
(1)
(2)
Figure 4. Test Circuit
V
M
= 1.5 V at V
CC
= 2.7 V
V
M
= 0.5
⋅V
CC
at V
CC
=1.2 V, 2.0 V, 3.0 V, 4.5 V
V
1
= V
CC
at V
CC
=1.2 V, 2.0 V, 2.7 V, 4.5 V
V
1
= 2.7 V at V
CC
= 3.0 V
5
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