Burr Brown Products
from Texas Instruments
ADS8509
SLAS324A – OCTOBER 2004 – REVISED JUNE 2005
16-BIT 250-KSPS SERIAL CMOS SAMPLING ANALOG-TO-DIGITAL CONVERTER
FEATURES
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•
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•
•
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250-kHz Sampling Rate
4-V, 5-V, 10 V, ±3.33-V, ±5-V, and ±10-V Input
Ranges
±2.0 LSB Max INL
±1 LSB Max DNL, 16-Bit No Missing Codes
SPI Compatible Serial Output with
Daisy-Chain (TAG) Feature
Single 5-V Supply
Pin-Compatible With ADS7809 (Low Speed)
and 12-Bit ADS8508/7808
Uses Internal or External Reference
70-mW Typ Power Dissipation at 250 KSPS
20-Pin SO and 28-Pin SSOP Packages
Simple DSP Interface
DESCRIPTION
The ADS8509 is a complete 16-bit sampling
analog-to-digital (A/D) converter using state-of-the-art
CMOS structures. It contains a complete 16-bit,
capacitor-based, successive approximation register
(SAR) A/D converter with sample-and-hold, refer-
ence, clock, and a serial data interface. Data can be
output using the internal clock or can be
synchronized to an external data clock. The ADS8509
also provides an output synchronization pulse for
ease of use with standard DSP processors.
The ADS8509 is specified at a 250-kHz sampling rate
over the full temperature range. Precision resistors
provide various input ranges including ±10 V and 0 V
to 5 V, while the innovative design allows operation
from a single +5-V supply with power dissipation
under 100 mW.
The ADS8509 is available in 20-pin SO and 28-pin
SSOP packages, both fully specified for operation
over the industrial -40°C to 85°C temperature range.
APPLICATIONS
Industrial Process Control
Data Acquisition Systems
Digital Signal Processing
Medical Equipment
Instrumentation
Successive Approximation Register
Clock
EXT/INT
9.8 kΩ
R1
IN
4.9 kΩ
R2
IN
2.5 kΩ
R3
IN
CAP
Buffer
4 kΩ
REF
10 kΩ
CDAC
BUSY
Serial
Data
Out
&
Control
DATACLK
DATA
R/C
SB/BTC
CS
PWRD
Comparator
Internal
+2.5 V Ref
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2005, Texas Instruments Incorporated
ADS8509
www.ti.com
SLAS324A – OCTOBER 2004 – REVISED JUNE 2005
PACKAGE/ORDERING INFORMATION
(1)
PRODUCT
MINIMUM
RELATIVE
ACCURACY
(LSB)
NO
MISSING
CODE
MINIMUM
SINAD
(dB)
SPECIFICATION
TEMPERATURE
RANGE
PACKAGE
LEAD
PACKAGE
DESIGNATOR
ORDERING
NUMBER
ADS8509IBDW
ADS8509IBDWR
ADS8509IBDB
ADS8509IBDBR
ADS8509IDW
ADS8509IDWR
ADS8509IDB
ADS8509IDBR
TRANSPORT
MEDIA, QTY
Tube, 25
Tape and Reel, 2000
Tube, 50
Tape and Reel, 2000
Tube, 25
Tape and Reel, 2000
Tube, 50
Tape and Reel, 2000
SO-20
ADS8509IB
±2
16
85
-40°C to 85°C
SSOP-28
DW
DB
SO-20
ADS8509I
±3
15
83
-40°C to 85°C
SSOP-28
DW
DB
(1)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
UNIT
R1
IN
Analog inputs
R2
IN
R3
IN
REF
DGND, AGND2
Ground voltage differences
V
ANA
V
DIG
to V
ANA
V
DIG
Digital inputs
Maximum junction temperature
Storage temperature range
Internal power dissipation
Lead temperature (soldering, 1.6 mm from case 10 seconds)
(1)
All voltage values are with respect to network ground terminal.
±25 V
±25 V
±25 V
+V
ANA
+ 0.3 V to AGND2 - 0.3 V
±0.3 V
6V
0.3 V
6V
-0.3 V to +V
DIG
+ 0.3 V
165°C
–65°C to 150°C
700 mW
260°C
2
ADS8509
www.ti.com
SLAS324A – OCTOBER 2004 – REVISED JUNE 2005
ELECTRICAL CHARACTERISTICS
At T
A
= -40°C to 85°C, f
s
= 250 kHz, V
DIG
= V
ANA
= 5 V, using internal reference and 0.1%, 0.25 W fixed resistors (See
Figure 29
and
Figure 30)
(unless otherwise specified)
PARAMETER
Resolution
ANALOG INPUT
Voltage ranges
(1)
Impedance
(1)
Capacitance
THROUGHPUT SPEED
Conversion cycle
Throughput rate
DC ACCURACY
INL
DNL
Integral linearity error
Differential linearity error
No missing codes
Transition noise
(3)
Full-scale
error
(4) (5)
±10 V range
All other ranges
Int. Ref. with 0.1% external
fixed resistors
Int. Ref.
Ext. Ref. with 0.1% external
fixed resistors
Ext. Ref.
-10
±0.4
-5
-3
±2
1-µF Capacitor to CAP
-8
1
8
-8
5
3
-5
-3
±2
1
8
-0.5
-0.5
±2
10
-5
±0.4
5
3
mV
ppm/°C
ms
-0.5
-0.5
±7
0.5
0.5
-0.5
-0.5
±2
5
-3
-2
15
1
0.5
0.5
-0.5
-0.5
±7
0.5
0.5
3
2
-2
-1
16
1
0.5
0.5
2
1
LSB
(2)
LSB
Bits
LSB
%FSR
ppm/°C
%FSR
ppm/°C
mV
ppm/°C
Acquire and convert
250
4
250
4
µs
kHz
50
50
pF
TEST CONDITIONS
ADS8509I
MIN
TYP
MAX
16
MIN
ADS8509IB
TYP
MAX
16
UNIT
Bits
Full-scale error drift
Full-scale
error
(4) (5)
±10 V range
All other ranges
Full-scale error drift
Bipolar zero error
(4)
Bipolar zero error drift
Unipolar zero
error
(4)
10 V range
4 V and 5 V
range
Unipolar zero error drift
Recovery to rated accuracy after
power down
Power supply sensitivity
(V
DIG
= V
ANA
= V
D
)
AC ACCURACY
SFDR
THD
SINAD
Spurious-free dynamic range
Total harmonic distortion
Signal-to-(noise+distortion)
Signal-to-noise ratio
Full-power bandwidth
(7)
SAMPLING DYNAMICS
Aperture delay
Transient response
Overvoltage recovery
(8)
FS Step
f
I
= 20 kHz
f
I
= 20 kHz
f
I
= 20 kHz
–60-dB Input
f
I
= 20 kHz
83
83
90
+4.75 V < V
D
< +5.25 V
LSB
99
-98
88
30
88
500
-90
95
99
-98
-93
dB
(6)
dB
dB
dB
dB
kHz
85
88
32
SNR
86
88
500
5
2
150
5
2
150
ns
µs
ns
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
±10 V, 0 V to 5 V, etc. (see
Table 3)
LSB means least significant bit. For the ±10-V input range, one LSB is 305 µV.
Typical rms noise at worst case transitions and temperatures.
As measured with fixed resistors shown in
Figure 29
and
Figure 30.
Adjustable to zero with external potentiometer. Factory calibrated
with 0.1%, 0.25 W resistors.
For bipolar input ranges, full-scale error is the worst case of -full-scale or +full-scale uncalibrated deviation from ideal first and last code
transitions, divided by the transition voltage (not divided by the full-scale range) and includes the effect of offset error. For unipolar input
ranges, full-scale error is the deviation of the last code transition divided by the transition voltage. It also includes the effect of offset
error.
All specifications in dB are referred to a full-scale ±10-V input.
Full-power bandwidth is defined as the full-scale input frequency at which signal-to-(noise + distortion) degrades to 60 dB.
Recovers to specified performance after 2 x FS input overvoltage.
3
ADS8509
www.ti.com
SLAS324A – OCTOBER 2004 – REVISED JUNE 2005
ELECTRICAL CHARACTERISTICS (continued)
At T
A
= -40°C to 85°C, f
s
= 250 kHz, V
DIG
= V
ANA
= 5 V, using internal reference and 0.1%, 0.25 W fixed resistors (See
Figure 29
and
Figure 30)
(unless otherwise specified)
PARAMETER
REFERENCE
Internal reference voltage
Internal reference source current
(must use external buffer)
Internal reference drift
External reference voltage range
for specified linearity
External reference current drain
DIGITAL INPUTS
Logic levels
V
IL
V
IH
I
IL
I
IH
Low-level input voltage
High-level input voltage
Low-level input current
High-level input current
V
IL
= 0 V
V
IH
= 5 V
-0.3
2.0
0.8
V
DIG
+0.3 V
±10
±10
-0.3
2.0
0.8
V
DIG
+0.3 V
±10
±10
V
V
µA
µA
Ext. 2.5-V Ref.
2.3
No load
2.48
2.5
1
8
2.5
2.7
100
2.3
2.52
2.48
2.5
1
8
2.5
2.7
100
2.52
V
µA
ppm/°C
V
µA
TEST CONDITIONS
ADS8509I
MIN
TYP
MAX
MIN
ADS8509IB
TYP
MAX
UNIT
DIGITAL OUTPUTS
Data format (Serial 16-bits)
Data coding (Binary 2's comp-
lement or straight binary)
Pipeline delay (Conversion re-
sults only available after com-
pleted conversion.)
Data clock (Selectable for
internal or external data clock)
Internal clock (output only when
transmitting data)
External clock (can run continu-
ally but not recommended for
optimum performance)
V
OL
V
OH
Low-level output voltage
High-level output voltage
Leakage current
Output capacitance
POWER SUPPLIES
V
DIG
V
ANA
I
DIG
I
ANA
Digital input voltage
Analog input voltage
Digital input current
Analog input current
Must be
≤
V
ANA
4.75
4.75
5
5
4
10
5.25
5.25
4.75
4.75
5
5
4
10
5.25
5.25
V
V
mA
mA
EXT/INT Low
EXT/INT High
0.1
9
26
0.1
9
26
MHz
I
SINK
= 1.6 mA
I
SOURCE
= 500 µA
Hi-Z state,
V
OUT
= 0 V to V
DIG
Hi-Z state
4
±5
15
0.4
4
±5
15
0.4
V
V
µA
pF
MHz
POWER DISSIPATION
PWRD Low
PWRD High
TEMPERATURE RANGE
Specified performance
Derated performance
(9)
Storage
THERMAL RESISTANCE (Θ
JA
)
SSOP
SO
62
46
62
46
°C/W
°C/W
-40
-55
-65
85
125
150
-40
-55
-65
85
125
150
°C
°C
°C
f
S
= 250 kHz
70
50
100
70
50
100
mW
µW
(9)
The internal reference may not be started correctly beyond the industrial temperature range (-40°C to 85°C), therefore use of an
external reference is recommended.
4
ADS8509
www.ti.com
SLAS324A – OCTOBER 2004 – REVISED JUNE 2005
TIMING REQUIREMENTS, T
A
= –40°C to 85°C
PARAMETER
t
w1
t
d1
t
w2
t
d2
t
d3
t
conv
t
acq
t
conv
+ t
acq
t
d4
t
c1
t
d5
t
d6
t
c2
t
w3
t
w4
t
su1
t
su2
t
d7
t
d8
t
d9
t
d10
t
su3
t
d11
t
su3
t
h1
Pulse duration, convert
Delay time, BUSY from R/C low
Pulse duration, BUSY low
Delay time, BUSY, after end of conversion
Delay time, aperture
Conversion time
Acquisition time
Cycle time
Delay time, R/C Low to internal DATACLK output
Cycle time, internal DATACLK
Delay time, data valid to internal DATACLK high
Delay time, data valid after internal DATACLK low
Cycle time, external DATACLK
Pulse duration, external DATACLK high
Pulse duration, external DATACLK low
Setup time, R/C rise/fall to external DATACLK high
Setup time, R/C transition to CS transition
Delay time, SYNC, after external DATACLK high
Delay time, data valid
Delay time, CS to rising edge
Delay time, previous data available after CS, R/C low
Setup time, BUSY transition to first external DATACLK
Delay time, final external DATACLK to BUSY falling edge
Setup time, TAG valid
Hold time, TAG valid
0
2
15
20
35
15
15
15
10
3
2
10
2
5
1
35
20
t
C2
+ 5
270
110
35
35
1.8
4
5
5
2.2
MIN
40
6
20
2.2
TYP
MAX
UNIT
ns
ns
µs
ns
ns
µs
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
µs
ns
ns
DW PACKAGE
(TOP VIEW)
DB PACKAGE
(TOP VIEW)
20
VDIG
19
V
ANA
18
PWRD
17
BUSY
16
CS
15
R/C
14
TAG
13
DATA
12
DATACLK
11
SYNC
R1IN
1
AGND1
2
R2IN
3
R3IN
4
CAP
5
REF
6
AGND2
7
SB/BTC
8
EXT/INT
9
DGND
10
R1IN
1
AGND1
2
R2IN
3
R3IN
4
NC
5
CAP
6
REF
7
NC
8
AGND2
9
NC
10
NC
11
SB/BTC
12
EXT/INT
13
DGND
14
28
VDIG
27
V
ANA
26
PWRD
25
BUSY
24
CS
23
NC
22
NC
21
R/C
20
NC
19
TAG
18
NC
17
DATA
16
DATACLK
15
SYNC
5
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