PI3VDP411LST
Features
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Digital Video Level Shifter for dual mode DP signals
w/ inverting buffer for HPD signal
Description
Pericom Semiconductor’s PI3VDP411LST provides the ability
to use a Dual-mode Display Port transmitter in HDMI mode.
This
fl
exibility provides the user a choice of how to connect to
their favorite display. All signal paths accept AC coupled video
signals. The PI3VDP411LST converts this AC coupled signal
into an HDMI rev 1.3 compliant signal with proper signal swing.
This converstion is automatic and transparent to the user.
The PI3VDP411LST supports up to 2.5Gbps, which provides
12-bits of color depth per channel, as indicated in HDMI rev 1.3.
Converts low-swing AC coupled differential input to
HDMI rev 1.3 compliant open-drain current steering Rx
terminated differential output
HDMI level shifting operation up to 2.5Gbps per lane
(250MHz pixel clock)
Integrated 50-ohm termination resistors for AC-coupled
differential inputs.
Enable/Disable feature to turn off TMDS outputs to
enter low-power state.
Output slew rate control on TMDS outputs to minimize
EMI.
Transparent operation: no re-timing or configuration
required.
3.3 Power supply required.
Integrated ESD protection to 2kV Human Body on all
I/O pins
DDC level shifters
Inverting level shifter for HPD signal from HDMI/DVI
connector
Integrated pull-down on HPD_sink input guarantees
"input low" when no display is plugged in
Pin Configuration
HPD_SINK
SDA_SINK
SCL_SINK
DDC_EN
EQ_0
VCC3V
GND
GND
VCC3V
EQ_1
GND
OE#
GND
IN_D1-
IN_D1+
VCC3V
IN_D2-
IN_D2+
GND
IN_D3-
IN_D3+
VCC3V
IN_D4-
IN_D4+
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
GND
OUT_D1-
OUT_D1+
VCC3V
OUT_D2-
OUT_D2+
GND
OUT_D3-
OUT_D3+
VCC3V
OUT_D4-
OUT_D4+
38
39
40
41
42
43
44
45
46
47
48
1
2
3
4
5
6
7
8
9
10
11
48-pin QFN Pinout
19
18
17
16
15
14
13
12
GND
VCC3V
OC_0
OC_1
GND
SDA_SOURCE
VCC3V
OC_3
OC_2(REXT )
07-0191
HPD_SOURCE#
SCL_SOURCE
1
PS8906A
GND
08/28/07
PI3VDP411LST
Digital Video Level Shifter from AC coupled digital video input to
a DVI/HDMI transmitter w/ inverting buffer for HPD signal
Block Diagram
OE#
OUT_D4+
0V
OUT_D4-
IN_D4+
IN_D4-
Rx
OUT_D3+
0V
OUT_D3-
IN_D3+
IN_D3-
Rx
OUT_D2+
0V
OUT_D2-
IN_D2+
IN_D2-
Rx
OUT_D1+
0V
OUT_D1-
IN_D1+
IN_D1-
Rx
HPD_SOURCE#
HPD
HPD_SINK
SCL_SOURCE
SCL_SINK
SDA_SOURCE
SDA_SINK
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PS8906A
08/28/07
PI3VDP411LST
Digital Video Level Shifter from AC coupled digital video input to a
DVI/HDMI transmitter w/ inverting buffer for HPD signal
Table 1: Package Pinout
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
07-0191
Pin Name
GND
VCC3V
OC_0
OC_1
GND
OC_2(REXT)
HPD_SOURCE#
SDA_SOURCE
SCL_SOURCE
OC_3
VCC3V
GND
OUT_D4+
OUT_D4-
VCC3V
OUIT_D3+
OUT_D3-
GND
OUT_D2+
OUT_D2-
VCC3V
OUT_D1+
OUT_D1-
GND
OE#
VCC3V
GND
SCL_SINK
SDA_SINK
HPD_SINK
GND
DDC_EN
VCC3V
EQ_0
EQ_1
GND
GND
IN_D1-
IN_D1+
VCC3V
IN_D2-
IN_D2+
3
Pin Number
43
44
45
46
47
48
Pin Name
GND
IN_D3-
IN_D3+
VCC3V
IN_D4-
IN_D4+
PS8906A
08/28/07
PI3VDP411LST
Digital Video Level Shifter for dual mode DP
signals w/ inverting buffer for HPD signal
Note:
Stresses greater than those listed under MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this speci
fi
cation
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
Maximum Ratings
(Above which useful life may be im-
paired. For user guidelines, not tested.)
Storage Temperature.....................................–65°C to +150°C
Supply Voltage to Ground Potential.............–0.5V to +5V
DC Input Voltage..........................................–0.5V to V
DD
DC Output Current.......................................120mA
Power Dissipation.........................................1.0W
Table 2: Signal Descriptions
Pin Name
Type
OE#
5.5V tolerant low-voltage
single-ended input
Description
Enable for level shifter path
OE#
IN_D Termination OUT_D Outputs
1
>100KΩ
High-Z
0
50Ω
Active
Low-swing diff input from GMCH PCIE outputs.
IN_D4+ makes a differential pair with IN_D4–.
Low-swing diff input from GMCH PCIE outputs.
IN_D4– makes a differential pair with IN_D4+.
Low-swing diff input from GMCH PCIE outputs.
IN_D3+ makes a differential pair with IN_D3–.
Low-swing diff input from GMCH PCIE outputs.
IN_D3– makes a differential pair with IN_D3+.
Low-swing diff input from GMCH PCIE outputs.
IN_D2+ makes a differential pair with IN_D2–.
Low-swing diff input from GMCH PCIE outputs.
IN_D2– makes a differential pair with IN_D2+.
Low-swing diff input from GMCH PCIE outputs.
IN_D1+ makes a differential pair with IN_D1–.
Low-swing diff input from GMCH PCIE outputs.
IN_D1– makes a differential pair with IN_D1+.
HDMI 1.3 compliant TMDS output. OUT_D4+
makes a differential output signal with OUT_D4–.
HDMI 1.3 compliant TMDS output. OUT_D4–
makes a differential output signal with OUT_D4+.
HDMI 1.3 compliant TMDS output. OUT_D3+
makes a differential output signal with OUT_D3–.
HDMI 1.3 compliant TMDS output. OUT_D3–
makes a differential output signal with OUT_D3+.
IN_D4+
IN_D4–
IN_D3+
IN_D3–
IN_D2+
IN_D2–
IN_D1+
IN_D1–
OUT_D4+
OUT_D4–
OUT_D3+
OUT_D3–
Differential input
Differential input
Differential input
Differential input
Differential input
Differential input
Differential input
Differential input
TMDS Differential output
TMDS Differential output
TMDS Differential output
TMDS Differential output
07-0191
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PS8906A
08/28/07
PI3VDP411LST
Digital Video Level Shifter for dual mode DP
signals w/ inverting buffer for HPD signal
Pin Name
OUT_D2+
OUT_D2–
OUT_D1+
OUT_D1–
HPD_SINK
Type
TMDS Differential output
TMDS Differential output
TMDS Differential output
TMDS Differential output
5V tolerance single-ended input
Description
HDMI 1.3 compliant TMDS output. OUT_D2+ makes
a differential output signal with OUT_D2–.
HDMI 1.3 compliant TMDS output. OUT_D2– makes
a differential output signal with OUT_D2+.
HDMI 1.3 compliant TMDS output. OUT_D1+ makes
a differential output signal with OUT_D1–.
HDMI 1.3 compliant TMDS output. OUT_D1– makes
a differential output signal with OUT_D1+.
HPD_SOURCE#
SCL_SOURCE
SDA_SOURCE
SCL_SINK
SDA_SINK
DDC_EN
Low Frequency, 0V to 5V (nominal) input signal. This
signal comes from the HDMI connector. Voltage High
indicates "plugged" state; voltage low indicated
"unplugged". HPD_SINK is pulled down by an
integrated 100K ohm pulldown resistor.
1V buffer
Inverted buffer from 0V to 5V input signal. If input is
LOGIC HIGH, then output will be LOGIC LOW, with
VOL max of 0.1V max. If input is LOGIC LOW, then
output will be LOGIC LOW, with Voh of 0.8V min.
3.3V DDC Data I/O. Pulled up by external termina-
Single-ended 3.3V open-drain
DDC I/O
tion to 3.3V. Connected to SCL_SINK through volt-
age-limiting intergrated NMOS passgate.
Single-ended 3.3V open-drain
3.3V DDC Data I/O. Pulled up by external termination
DDC I/O
to 3.3V. Connected to SDA_SINK through voltage-
limiting intergrated NMOS passgate.
5V DDC Clock I/O. Pulled up by external termination
Single-ended 5V open-drain
DDC I/O
to 5V. Connected to SCL_SOURCE through voltage-
limiting integrated NMOS passgate.
Single-ended 5V open-drain
5V DDC Data I/O. Pulled up by external termination
DDC I/O
to 5V. Connected to SDA_SOURCE through voltage-
limiting integrated NMOS passgate.
5.0V tolerant Single-ended input Enables bias voltage to the DDC passgate level shifter
gates. (May be implemented as a bias voltage connec-
tion to the DDC pass gates themselves.)
DDC_EN
Passgate
0V
Disabled
Enabled
3.3V
3.3V DC Supply
3.3V single-ended control input
3.3V ± 10%
Acceptable connections to OC_1 (REXT) pin are: Re-
sistor to GND; Resistor to 3.3V; NC. (Resistor should
be 0-ohm).
VCC3V
OC_2
(1)
(REXT)
Note:
1) internal 100Kohm pull-up
07-0191
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PS8906A
08/28/07
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